GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/pineview: Tidy up comments and cosmetics 

Remove some unneeded newlines, add some commas for consistency and
relocate comments to match the code.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I0ac18a692bf613c75083c4aa1860e0a9f07e68d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-07-07 03:00:24 +02:00
parent f67bf49ead
commit 4d962b2ecf
3 changed files with 9 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/northbridge/intel/pineview/acpi/hostbridge.asl
View File

@ -24,7 +24,7 @@ Device (MCHC)
, 13,
MHBR, 22, /* MCHBAR */
Offset (0x60), /* PCIec BAR */
Offset (0x60), /* PCIe BAR */
PXEN, 1, /* Enable */
PXSZ, 2, /* BAR size */
, 23,
@ -35,7 +35,7 @@ Device (MCHC)
, 11, /*
DMBR, 20, /* DMIBAR */
// ...
/* ... */
Offset (0x90), /* PAM0 */
, 4,
@ -78,13 +78,9 @@ Device (MCHC)
Offset (0xb0), /* Top of Low Used Memory */
, 4,
TLUD, 12,
}
}
/* Current Resource Settings */
Name (MCRS, ResourceTemplate()
{
/* Bus Numbers */
@ -199,6 +195,7 @@ Name (MCRS, ResourceTemplate()
0x00005000,,, TPMR)
})
/* Current Resource Settings */
Method (_CRS, 0, Serialized)
{
/* Find PCI resource area in MCRS */
@ -206,7 +203,8 @@ Method (_CRS, 0, Serialized)
CreateDwordField(MCRS, ^PM01._MAX, PMAX)
CreateDwordField(MCRS, ^PM01._LEN, PLEN)
/* Fix up PCI memory region:
/*
* Fix up PCI memory region:
* Enter actual TOLUD. The TOLUD register contains bits 27-31 of
* the top of memory address.
*/

5
src/northbridge/intel/pineview/acpi/peg.asl
View File

@ -12,16 +12,15 @@ Device (PEGP)
Package() { 0x0000ffff, 0, 0, 16 },
Package() { 0x0000ffff, 1, 0, 17 },
Package() { 0x0000ffff, 2, 0, 18 },
Package() { 0x0000ffff, 3, 0, 19 }
Package() { 0x0000ffff, 3, 0, 19 },
})
} Else {
Return (Package() {
Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
})
}
}
}

4
src/northbridge/intel/pineview/acpi/pineview.asl
View File

@ -10,9 +10,7 @@ Device (PDRC)
Name (_HID, EISAID("PNP0C02"))
Name (_UID, 1)
/* This does not seem to work correctly yet - set values statically for
* now.
*/
/* This does not seem to work correctly yet - set values statically for now. */
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, DEFAULT_RCBA, 0x00004000)