soc/intel/cannonlake: Allow Audio DSP OSC qualification for low power idle

With Audio DSP OSC qualification disabled from S0ix criteria.
S0ix is achieved before the DSP is suspended. When driver tries
to suspend DSP its already turned off.

BUG=b:139481313

Change-Id: I20b793b95483af03ce4ae068ac07864a9e90d39b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37604
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2019-12-09 16:05:52 +05:30 committed by Patrick Georgi
parent d8663e0fc6
commit 4d9d3f164d
3 changed files with 16 additions and 1 deletions

View File

@ -59,8 +59,13 @@ struct soc_intel_cannonlake_config {
uint32_t gen3_dec; uint32_t gen3_dec;
uint32_t gen4_dec; uint32_t gen4_dec;
/* S0ix configuration */
/* Enable S0iX support */ /* Enable S0iX support */
int s0ix_enable; int s0ix_enable;
/* Enable Audio DSP oscillator qualification for S0ix */
uint8_t cppmvric2_adsposcdis;
/* Enable DPTF support */ /* Enable DPTF support */
int dptf_enable; int dptf_enable;

View File

@ -91,11 +91,18 @@ static void pch_finalize(void)
write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8); write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
} }
/* Disable XTAL shutdown qualification for low power idle. */
if (config->s0ix_enable) { if (config->s0ix_enable) {
/* Disable XTAL shutdown qualification for low power idle. */
reg32 = read32(pmcbase + CPPMVRIC); reg32 = read32(pmcbase + CPPMVRIC);
reg32 |= XTALSDQDIS; reg32 |= XTALSDQDIS;
write32(pmcbase + CPPMVRIC, reg32); write32(pmcbase + CPPMVRIC, reg32);
if (config->cppmvric2_adsposcdis) {
/* Enable Audio DSP OSC qualification for S0ix */
reg32 = read32(pmcbase + CPPMVRIC2);
reg32 &= ~ADSPOSCDIS;
write32(pmcbase + CPPMVRIC2, reg32);
}
} }
pch_handle_sideband(config); pch_handle_sideband(config);

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@ -156,6 +156,9 @@
#define CPPMVRIC 0x1B1C #define CPPMVRIC 0x1B1C
#define XTALSDQDIS (1 << 22) #define XTALSDQDIS (1 << 22)
#define CPPMVRIC2 0x1B4C
#define ADSPOSCDIS (1 << 22)
#define IRQ_REG ACTL #define IRQ_REG ACTL
#define SCI_IRQ_ADJUST 0 #define SCI_IRQ_ADJUST 0
#define ACTL 0x1BD8 #define ACTL 0x1BD8