northbridge/amd/amdk8: Remove commented code
Change-Id: Ifd6aefa6c046d100a5388a24a7d23cbd77905a85 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16893 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS
Martin Roth
parent
11302f38cd
commit
4da1aa8561
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@ -147,49 +147,19 @@ static unsigned long acpi_fill_slit(unsigned long current)
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3, 4, 2, 3, 1, 2, 0, 1,
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4, 4, 3, 2, 2, 1, 1, 0 };
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// u8 outer_node[8];
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u8 *p = (u8 *)current;
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int nodes = sysconf.nodes;
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int i,j;
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memset(p, 0, 8+nodes*nodes);
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// memset((u8 *)outer_node, 0, 8);
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*p = (u8) nodes;
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p += 8;
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#if 0
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for (i = 0; i < sysconf.hc_possible_num; i++) {
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if ((sysconf.pci1234[i]&1) !=1) continue;
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outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node
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}
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#endif
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for (i = 0; i < nodes; i++) {
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for (j = 0; j < nodes; j++) {
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if (i == j) {
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p[i*nodes+j] = 10;
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} else {
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#if 0
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int k;
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u8 latency_factor = 0;
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int k_start, k_end;
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if (i < j) {
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k_start = i;
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k_end = j;
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} else {
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k_start = j;
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k_end = i;
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}
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for (k = k_start; k <= k_end; k++) {
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if (outer_node[k]) {
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latency_factor = 1;
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break;
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}
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}
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p[i*nodes+j] = hops_8[i*nodes+j] * 2 + latency_factor + 10;
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#else
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p[i*nodes+j] = hops_8[i*nodes+j] * 2 + 10;
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#endif
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}
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}
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@ -149,21 +149,6 @@ static void disable_probes(void)
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}
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#if 0
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static void enable_apic_ext_id(u8 node)
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{
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#if CONFIG_ENABLE_APIC_EXT_ID
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#warning "FIXME Is the right place to enable apic ext id here?"
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u32 val;
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val = pci_read_config32(NODE_HT(node), 0x68);
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val |= (HTTC_APIC_EXT_SPUR | HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST);
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pci_write_config32(NODE_HT(node), 0x68, val);
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#endif
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}
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#endif
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static void enable_routing(u8 node)
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{
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u32 val;
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@ -566,13 +551,6 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif
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val_s-=link_connection(temp, source-2); /* -down*/
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} else {
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#if CROSS_BAR_47_56
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#if 0
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if (source == 7) {
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val_s-=link_connection(temp, 6); // for 7,2 via 5
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} else if (source == 6) {
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val_s-=link_connection(temp, 7); // for 6,3 via 4
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} else
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#endif
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if (source < gateway) { // for 5, 4 via 7
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val_s-=link_connection(temp, source-2);
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} else
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@ -743,10 +721,6 @@ static unsigned setup_smp2(void)
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setup_remote_node(1); /* Setup the regs on the remote node */
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rename_temp_node(1); /* Rename Node 7 to Node 1 */
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enable_routing(1); /* Enable routing on Node 1 */
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#if 0
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/*don't need and it is done by clear_dead_links */
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clear_temp_row(0);
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#endif
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return nodes;
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}
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@ -910,13 +884,6 @@ static unsigned setup_smp4(void)
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#endif
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setup_row_indirect_group(conn4_2, ARRAY_SIZE(conn4_2));
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#if 0
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/*We need to do sth to reverse work for setup_temp_row (0,1) (1,3) */
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/* it will be done by clear_dead_links */
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clear_temp_row(0);
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clear_temp_row(1);
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#endif
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return nodes;
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}
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@ -1111,15 +1078,6 @@ static unsigned setup_smp6(void)
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setup_row_indirect_group(conn6_4, ARRAY_SIZE(conn6_4));
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#if 0
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/* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
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* It will be done by clear_dead_links
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*/
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for (byte = 0; byte < 4; byte++) {
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clear_temp_row(byte);
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}
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#endif
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return nodes;
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}
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@ -1260,12 +1218,6 @@ static unsigned setup_smp8(void)
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#endif
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print_linkn("\t-->(5,6) link=", byte);
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setup_row_direct(5, 6, byte);
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#if 0
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setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
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for (byte = 0; byte < 4; byte+=2) {
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setup_temp_row(byte+1,byte+3);
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}
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#endif
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setup_temp_row(5,6);
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verify_connection(7);
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@ -555,11 +555,6 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
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if (!mask) break;
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#if 0
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/* cpu_relax */
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__asm__ __volatile__("rep;nop": : :"memory");
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#endif
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i++;
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i%=sysinfo->nodes;
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}
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@ -27,44 +27,6 @@
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#include <cpu/amd/amdk8_sysconf.h>
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#if 0
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unsigned node_link_to_bus(unsigned node, unsigned link)
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{
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device_t dev;
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unsigned reg;
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dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
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if (!dev) {
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return 0;
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}
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for (reg = 0xE0; reg < 0xF0; reg += 0x04) {
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uint32_t config_map;
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unsigned dst_node;
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unsigned dst_link;
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unsigned bus_base;
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config_map = pci_read_config32(dev, reg);
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if ((config_map & 3) != 3) {
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continue;
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}
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dst_node = (config_map >> 4) & 7;
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dst_link = (config_map >> 8) & 3;
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bus_base = (config_map >> 16) & 0xff;
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#if 0
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printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
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dst_node, dst_link, bus_base,
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reg, config_map);
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#endif
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if ((dst_node == node) && (dst_link == link))
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{
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return bus_base;
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}
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}
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return 0;
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}
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#endif
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/*
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* Why we need the pci1234[] array
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*
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@ -56,13 +56,6 @@ static uint8_t ht_lookup_slave_capability(pci_devfn_t dev)
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return ht_lookup_capability(dev, 0); // Slave/Primary Interface Block Format
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}
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#if 0
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static uint8_t ht_lookup_host_capability(pci_devfn_t dev)
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{
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return ht_lookup_capability(dev, 1); // Host/Secondary Interface Block Format
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}
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#endif
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static void ht_collapse_previous_enumeration(uint8_t bus, unsigned offset_unitid)
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{
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pci_devfn_t dev;
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@ -470,40 +463,6 @@ end_of_chain:;
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}
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#if 0
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#if CONFIG_RAMINIT_SYSINFO
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static void ht_setup_chain(pci_devfn_t udev, unsigned upos,
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struct sys_info *sysinfo)
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#else
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static int ht_setup_chain(pci_devfn_t udev, unsigned upos)
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#endif
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{
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unsigned offset_unitid = 0;
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#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
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offset_unitid = 1;
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#endif
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/* Assumption the HT chain that is bus 0 has the HT I/O Hub on it.
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* On most boards this just happens. If a CPU has multiple
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* non Coherent links the appropriate bus registers for the
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* links needs to be programed to point at bus 0.
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*/
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/* Make certain the HT bus is not enumerated */
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ht_collapse_previous_enumeration(0, 0);
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#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
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offset_unitid = 1;
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#endif
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#if CONFIG_RAMINIT_SYSINFO
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ht_setup_chainx(udev, upos, 0, offset_unitid, sysinfo);
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#else
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return ht_setup_chainx(udev, upos, 0, offset_unitid);
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#endif
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}
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#endif
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static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val)
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{
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uint32_t dword, dword_old;
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@ -563,12 +563,6 @@ static void amdk8_set_resources(device_t dev)
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static void mcf0_control_init(struct device *dev)
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{
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#if 0
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printk(BIOS_DEBUG, "NB: Function 0 Misc Control.. ");
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#endif
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#if 0
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printk(BIOS_DEBUG, "done.\n");
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#endif
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}
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static struct device_operations northbridge_operations = {
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@ -902,8 +896,6 @@ static void amdk8_domain_set_resources(device_t dev)
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reset_memhole = 0;
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}
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//mmio_basek = 3*1024*1024; // for debug to meet boundary
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if (reset_memhole) {
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if (mem_hole.node_id!=-1) { // We need to select CONFIG_HW_MEM_HOLE_SIZEK for raminit, it can not make hole_startk to some basek too....!
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// We need to reset our Mem Hole, because We want more big HOLE than we already set
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@ -965,8 +957,6 @@ static void amdk8_domain_set_resources(device_t dev)
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printk(BIOS_DEBUG, "node %d : uma_memory_base/1024=0x%08llx, mmio_basek=0x%08lx, basek=0x%08x, limitk=0x%08x\n", i, uma_memory_base >> 10, mmio_basek, basek, limitk);
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if ((uma_memory_base >> 10) < mmio_basek)
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printk(BIOS_ALERT, "node %d: UMA memory starts below mmio_basek\n", i);
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#else
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// printk(BIOS_DEBUG, "node %d : mmio_basek=%08x, basek=%08x, limitk=%08x\n", i, mmio_basek, basek, limitk); //yhlu
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#endif
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/* See if I need to split the region to accommodate pci memory space */
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@ -20,7 +20,6 @@
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void setup_resource_map(const unsigned int *register_values, int max)
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{
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int i;
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// printk(BIOS_DEBUG, "setting up resource map....");
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for (i = 0; i < max; i += 3) {
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pci_devfn_t dev;
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unsigned where;
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@ -32,7 +31,6 @@ void setup_resource_map(const unsigned int *register_values, int max)
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reg |= register_values[i+2];
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pci_write_config32(dev, where, reg);
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}
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// printk(BIOS_DEBUG, "done.\n");
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}
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static int controller_present(const struct mem_controller *ctrl)
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@ -519,7 +517,6 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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int max;
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if (!controller_present(ctrl)) {
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// printk(BIOS_DEBUG, "No memory controller present\n");
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return;
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}
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printk(BIOS_SPEW, "setting up CPU%02x northbridge registers\n", ctrl->node_id);
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@ -965,7 +962,6 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
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if (is_dual_channel(ctrl)) {
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/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
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if ((bits == 3) && (common_size == (1 << (32 - 3)))) {
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// printk(BIOS_DEBUG, "8 4GB chip selects cannot be interleaved\n");
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return 0;
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}
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csbase_inc <<=1;
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@ -975,7 +971,6 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
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csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
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if (is_dual_channel(ctrl)) {
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if ((bits == 3) && (common_cs_mode > 8)) {
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// printk(BIOS_DEBUG, "8 cs_mode > 8 chip selects cannot be interleaved\n");
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return 0;
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}
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csbase_inc <<=1;
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@ -1469,9 +1464,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_
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}
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/* now the lookup, decode the max speed DDR400_2T etc */
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dloading = dimm_loading_config[dpos][rpos] & DDR_MASK;
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#if 0
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printk(BIOS_DEBUG, "XXX %x %x dload %x 2T %x\n", dpos,rpos, dloading, dimm_loading_config[dpos][rpos] & DDR_2T);
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#endif
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hw_error:
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if (dloading != 0) {
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/* we have valid combination check the restrictions */
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@ -1671,14 +1664,6 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
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/* Update DRAM Config High with our selected memory speed */
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value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
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value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
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#if 0
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/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/
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if (!is_cpu_pre_e0()) {
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if (min_cycle_time == 0x50) {
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value |= 1<<31;
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}
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}
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#endif
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value |= result.param->dch_memclk;
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pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
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@ -2189,7 +2174,6 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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long dimm_mask;
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#if 1
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if (!controller_present(ctrl)) {
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// printk(BIOS_DEBUG, "No memory controller present\n");
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return;
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}
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#endif
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@ -2453,11 +2437,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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if (!is_cpu_pre_c0()) {
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/* Wait until it is safe to touch memory */
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#if 0
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/* the registers are marked read-only but code zeros them */
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dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
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pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
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#endif
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do {
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dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
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} while (((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) ||
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@ -701,15 +701,6 @@ index:
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printk(BIOS_SPEW, "done.\n");
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}
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#if 0
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static int is_dual_channel(const struct mem_controller *ctrl)
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{
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uint32_t dcl;
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dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
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return dcl & DCL_Width128;
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}
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#endif
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static int is_opteron(const struct mem_controller *ctrl)
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{
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/* Test to see if I am an Opteron. M2 and S1G1 support dual
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@ -725,19 +716,6 @@ static int is_opteron(const struct mem_controller *ctrl)
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return !!(nbcap & NBCAP_128Bit);
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}
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#if 0
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static int is_registered(const struct mem_controller *ctrl)
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{
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/* Test to see if we are dealing with registered SDRAM.
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* If we are not registered we are unbuffered.
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* This function must be called after spd_handle_unbuffered_dimms.
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*/
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uint32_t dcl;
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dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
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return !(dcl & DCL_UnBuffDimm);
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}
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#endif
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static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
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{
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/* Calculate the log base 2 size of a DIMM in bits */
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@ -776,7 +754,6 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
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/* number of physical banks */
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value = spd_read_byte(device, SPD_MOD_ATTRIB_RANK);
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if (value < 0) goto hw_err;
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/* value >>= SPD_MOD_ATTRIB_RANK_NUM_SHIFT; */
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value &= SPD_MOD_ATTRIB_RANK_NUM_MASK;
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value += SPD_MOD_ATTRIB_RANK_NUM_BASE; // 0-->1, 1-->2, 3-->4
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/*
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@ -1350,16 +1327,6 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
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}
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if (is_opteron(ctrl)) {
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#if 0
|
||||
if (registered != (meminfo->dimm_mask & ((1 << DIMM_SOCKETS)-1))) {
|
||||
meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS)); //disable unbuffered dimm
|
||||
// die("Mixed buffered and registered dimms not supported");
|
||||
}
|
||||
//By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
|
||||
if (!registered) {
|
||||
die("Unbuffered Dimms not supported on Opteron");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1524,7 +1491,6 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i
|
|||
dcm |= DCM_Mode64BitMux;
|
||||
pci_write_config32(ctrl->f2, DRAM_CTRL_MISC, dcm);
|
||||
dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
|
||||
//dcl |= DCL_BurstLength32; /* 32byte mode for channelB only */
|
||||
pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
|
||||
meminfo->is_64MuxMode = 1;
|
||||
} else {
|
||||
|
|
@ -2080,7 +2046,6 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me
|
|||
|
||||
old_clocks = ((dtl >> TT_SHIFT) & TT_MASK) + TT_BASE;
|
||||
if (old_clocks >= clocks) { //some one did it?
|
||||
// clocks = old_clocks;
|
||||
return 1;
|
||||
}
|
||||
dtl &= ~(TT_MASK << TT_SHIFT);
|
||||
|
|
|
|||
|
|
@ -1694,13 +1694,6 @@ static void setup_mtrr_dqs(unsigned tom_k, unsigned tom2_k)
|
|||
{
|
||||
msr_t msr;
|
||||
|
||||
#if 0
|
||||
//still enable from cache_as_ram.inc
|
||||
msr = rdmsr(SYSCFG_MSR);
|
||||
msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
|
||||
wrmsr(SYSCFG_MSR,msr);
|
||||
#endif
|
||||
|
||||
//[0,512k), [512k, 640k)
|
||||
msr.hi = 0x1e1e1e1e;
|
||||
msr.lo = msr.hi;
|
||||
|
|
@ -2037,8 +2030,6 @@ out:
|
|||
static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct sys_info *sysinfox)
|
||||
{
|
||||
dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the output tidy
|
||||
// memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 * 8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8);
|
||||
// memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9], &sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9);
|
||||
sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid];
|
||||
|
||||
}
|
||||
|
|
@ -2054,15 +2045,7 @@ static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sy
|
|||
wait_till_sysinfo_in_ram(); // use pci to get it
|
||||
|
||||
if (sysinfox->mem_trained[nodeid] == 0x80) {
|
||||
#if 0
|
||||
sysinfo->tom_k = sysinfox->tom_k;
|
||||
sysinfo->tom2_k = sysinfox->tom2_k;
|
||||
sysinfo->meminfo[nodeid].is_Width128 = sysinfox->meminfo[nodeid].is_Width128;
|
||||
sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid];
|
||||
memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid], sizeof(struct mem_controller));
|
||||
#else
|
||||
memcpy(sysinfo, sysinfox, sizeof(*sysinfo));
|
||||
#endif
|
||||
set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the ap's tom consistent with bsp's
|
||||
printk(BIOS_DEBUG, "CODE IN ROM AND RUN ON NODE: %02x\n", nodeid);
|
||||
train_ram(nodeid, sysinfo, sysinfox);
|
||||
|
|
|
|||
|
|
@ -56,10 +56,6 @@ static uint32_t pci_read_config32(device_t dev, unsigned where)
|
|||
(pci_register[addr + 1] << 8) |
|
||||
(pci_register[addr + 2] << 16) |
|
||||
(pci_register[addr + 3] << 24);
|
||||
|
||||
#if 0
|
||||
printk(BIOS_DEBUG, "pcir32(%08x): %08x\n", addr, value);
|
||||
#endif
|
||||
return value;
|
||||
|
||||
}
|
||||
|
|
@ -87,10 +83,6 @@ static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
|
|||
pci_register[addr + 1] = (value >> 8) & 0xff;
|
||||
pci_register[addr + 2] = (value >> 16) & 0xff;
|
||||
pci_register[addr + 3] = (value >> 24) & 0xff;
|
||||
|
||||
#if 0
|
||||
printk(BIOS_DEBUG, "pciw32(%08x, %08x)\n", addr, value);
|
||||
#endif
|
||||
}
|
||||
|
||||
#define PCI_DEV_INVALID (0xffffffffU)
|
||||
|
|
@ -277,10 +269,6 @@ static int spd_read_byte(unsigned device, unsigned address)
|
|||
result = spd_data[(device << 8) | address];
|
||||
}
|
||||
}
|
||||
#if 0
|
||||
printk(BIOS_DEBUG, "spd_read_byte(%08x, %08x) -> %08x\n",
|
||||
device, address, result);
|
||||
#endif
|
||||
if (spd_count >= spd_fail_count) {
|
||||
result = -1;
|
||||
}
|
||||
|
|
@ -355,10 +343,6 @@ static void reset_tests(void)
|
|||
/* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
|
||||
(NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
|
||||
NBCAP_MEMCTRL);
|
||||
|
||||
#if 0
|
||||
pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void test1(void)
|
||||
|
|
@ -367,22 +351,7 @@ static void test1(void)
|
|||
|
||||
memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
|
||||
#if 0
|
||||
memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256);
|
||||
|
||||
memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256);
|
||||
#endif
|
||||
|
||||
raminit_main();
|
||||
|
||||
#if 0
|
||||
printk(BIOS_DEBUG, "spd_count: %d\n", spd_count);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -22,12 +22,6 @@ void setup_resource_map_offset(const unsigned int *register_values, int max, uns
|
|||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2] + offset_io_base;
|
||||
pci_write_config32(dev, where, reg);
|
||||
#if 0
|
||||
reg = pci_read_config32(register_values[i]);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2] & ~register_values[i+1];
|
||||
pci_write_config32(register_values[i], reg);
|
||||
#endif
|
||||
}
|
||||
#if RES_DEBUG
|
||||
printk(BIOS_DEBUG, "done.\n");
|
||||
|
|
@ -94,20 +88,6 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
|
|||
outl(reg, where);
|
||||
}
|
||||
break;
|
||||
#if 0
|
||||
case RES_MEM_IO: //mem
|
||||
{
|
||||
unsigned where;
|
||||
unsigned long reg;
|
||||
where = register_values[i+1];
|
||||
reg = read32(where);
|
||||
reg &= register_values[i+2];
|
||||
reg |= register_values[i+3];
|
||||
write32(where, reg);
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
|
||||
} // switch
|
||||
|
||||
|
||||
|
|
@ -122,63 +102,3 @@ static inline void setup_resource_map_x(const unsigned int *register_values, int
|
|||
{
|
||||
setup_resource_map_x_offset(register_values, max, 0, 0);
|
||||
}
|
||||
|
||||
#if 0
|
||||
static void setup_io_resource_map(const unsigned int *register_values, int max)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < max; i += 3) {
|
||||
unsigned where;
|
||||
unsigned long reg;
|
||||
|
||||
where = register_values[i];
|
||||
#if 0
|
||||
udelay(2000);
|
||||
printk(BIOS_DEBUG, "%04x", where);
|
||||
#endif
|
||||
|
||||
reg = inl(where);
|
||||
#if 0
|
||||
udelay(2000);
|
||||
printk(BIOS_DEBUG, "=%08x", reg);
|
||||
#endif
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2];
|
||||
|
||||
#if 0
|
||||
udelay(2000);
|
||||
printk(BIOS_DEBUG, " <- %08x", reg);
|
||||
#endif
|
||||
outl(reg, where);
|
||||
#if 0
|
||||
udelay(2000);
|
||||
reg = inl(where);
|
||||
printk(BIOS_DEBUG, " -> %08x\n", reg);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
static void setup_mem_resource_map(const unsigned int *register_values, int max)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < max; i += 3) {
|
||||
unsigned where;
|
||||
unsigned long reg;
|
||||
#if 0
|
||||
prink(BIOS_DEBUG, "%08x <- %08x\n",
|
||||
register_values[i], register_values[i+2]);
|
||||
#endif
|
||||
where = register_values[i];
|
||||
reg = read32(where);
|
||||
reg &= register_values[i+1];
|
||||
reg |= register_values[i+2];
|
||||
write32(where, reg);
|
||||
#if 0
|
||||
reg = read32(where);
|
||||
prink(BIOS_DEBUG, " RB %08x\n", reg);
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue