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mb/google/skyrim: Add DXIO descriptors 

Add Skyrim DXIO descriptors using info from AMD and skyrim bouard
shematics.

BUG=b:225179599
TEST=Boots to OS on Skyrim Board

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Jon Murphy 2022-03-17 11:05:54 -06:00 committed by Felix Held
parent 69c3611226
commit 4dac96d968
3 changed files with 83 additions and 3 deletions
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77
src/mainboard/google/skyrim/port_descriptors.c
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@ -1,11 +1,86 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h>
#include <soc/gpio.h>
#include <soc/platform_descriptors.h> #include <soc/platform_descriptors.h>
#include <types.h> #include <types.h>
static const fsp_dxio_descriptor skyrim_sbna_dxio_descriptors[] = {
{ /* WLAN */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 0,
.end_logical_lane = 0,
.device_number = PCI_SLOT(WLAN_DEVFN),
.function_number = PCI_FUNC(WLAN_DEVFN),
.link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
.link_aspm = 2,
.link_hotplug = 3,
.clk_req = CLK_REQ2,
},
{ /* SD */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 1,
.end_logical_lane = 1,
.device_number = PCI_SLOT(SD_DEVFN),
.function_number = PCI_FUNC(SD_DEVFN),
.link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
.gpio_group_id = GPIO_27,
.clk_req = CLK_REQ1,
},
{ /* SSD */
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 2,
.end_logical_lane = 3,
.device_number = PCI_SLOT(NVME_DEVFN),
.function_number = PCI_FUNC(NVME_DEVFN),
.link_speed_capability = GEN3,
.turn_off_unused_lanes = true,
.link_aspm = 2,
.link_hotplug = 3,
.gpio_group_id = GPIO_6,
.clk_req = CLK_REQ0,
},
};
static const fsp_ddi_descriptor skyrim_sbna_ddi_descriptors[] = {
{ /* DDI0 - eDP */
.connector_type = DDI_EDP,
.aux_index = DDI_AUX1,
.hdp_index = DDI_HDP1
},
{ /* DDI1 - DP (type C) */
.connector_type = DDI_DP,
.aux_index = DDI_AUX2,
.hdp_index = DDI_HDP2
},
{ /* DDI2 - DP (type C) */
.connector_type = DDI_DP,
.aux_index = DDI_AUX3,
.hdp_index = DDI_HDP3,
},
{ /* DDI3 - DP (type C) */
.connector_type = DDI_DP,
.aux_index = DDI_AUX4,
.hdp_index = DDI_HDP4,
},
{ /* DDI4 - Unused */
.connector_type = DDI_UNUSED_TYPE,
.aux_index = DDI_AUX5,
.hdp_index = DDI_HDP5,
},
};
void mainboard_get_dxio_ddi_descriptors( void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{ {
/* TODO: Initialize DXIO and DDI descriptors */ *dxio_descs = skyrim_sbna_dxio_descriptors;
*dxio_num = ARRAY_SIZE(skyrim_sbna_dxio_descriptors);
*ddi_descs = skyrim_sbna_ddi_descriptors;
*ddi_num = ARRAY_SIZE(skyrim_sbna_ddi_descriptors);
} }

3
src/mainboard/google/skyrim/variants/baseboard/devicetree.cb
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@ -62,8 +62,7 @@ chip soc/amd/sabrina
end end
end end
device ref gpp_bridge_1 on end # SD device ref gpp_bridge_1 on end # SD
device ref gpp_bridge_2 on end # WWAN device ref gpp_bridge_2 on end # NVMe
device ref gpp_bridge_3 on end # NVMe
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX) device ref gfx on end # Internal GPU (GFX)

6
src/mainboard/google/skyrim/variants/baseboard/include/baseboard/variants.h
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@ -4,6 +4,12 @@
#define __BASEBOARD_VARIANTS_H__ #define __BASEBOARD_VARIANTS_H__
#include <amdblocks/gpio.h> #include <amdblocks/gpio.h>
#include <soc/pci_devs.h>
#include <platform_descriptors.h>
#define WLAN_DEVFN PCIE_GPP_2_0_DEVFN
#define SD_DEVFN PCIE_GPP_2_1_DEVFN
#define NVME_DEVFN PCIE_GPP_2_2_DEVFN
/* /*
* This function provides base GPIO configuration table. It is typically provided by * This function provides base GPIO configuration table. It is typically provided by