diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc
index fe66d43dbe..c7b2e16c4b 100644
--- a/src/soc/nvidia/tegra124/Makefile.inc
+++ b/src/soc/nvidia/tegra124/Makefile.inc
@@ -26,6 +26,7 @@ romstage-y += early_display.c
 romstage-y += dma.c
 romstage-y += i2c.c
 romstage-y += monotonic_timer.c
+romstage-y += power.c
 romstage-y += sdram.c
 romstage-y += sdram_lp0.c
 romstage-y += spi.c
diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c
index a3cf5ef63b..760d058712 100644
--- a/src/soc/nvidia/tegra124/power.c
+++ b/src/soc/nvidia/tegra124/power.c
@@ -85,3 +85,8 @@ void power_ungate_cpu(void)
 	// Ungate power to CPU0 in the fast cluster.
 	power_ungate_partition(POWER_PARTID_CE0);
 }
+
+int power_reset_status(void)
+{
+	return read32(&pmc->rst_status) & 0x7;
+}
diff --git a/src/soc/nvidia/tegra124/power.h b/src/soc/nvidia/tegra124/power.h
index 6454699a9c..130ed2525a 100644
--- a/src/soc/nvidia/tegra124/power.h
+++ b/src/soc/nvidia/tegra124/power.h
@@ -26,4 +26,15 @@ void power_enable_cpu_rail(void);
 
 void power_ungate_cpu(void);
 
+// power_reset_status returns one of the following possible sources for the
+// most recent reset.
+enum {
+	POWER_RESET_POR = 0,
+	POWER_RESET_WATCHDOG = 1,
+	POWER_RESET_SENSOR = 2,
+	POWER_RESET_SW_MAIN = 3,
+	POWER_RESET_LP0 = 4
+};
+int power_reset_status(void);
+
 #endif	/* __SOC_NVIDIA_TEGRA124_POWER_H__ */