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northbridge/amd/amdfam10: Fix poor performance on Family 15h CPUs 

Change-Id: I193749bc767b7c1139de7cd67622a7b03298009b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12031
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Timothy Pearson 2015-08-07 19:06:09 -05:00 committed by Stefan Reinauer
parent 167c03ad4a
commit 4dc6cabd36
2 changed files with 23 additions and 2 deletions
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4
src/northbridge/amd/amdfam10/nb_control.c
View File

@ -60,10 +60,10 @@ static void nb_control_init(struct device *dev)
pci_write_config32(dev, 0xe0, dword); pci_write_config32(dev, 0xe0, dword);
/* Configure northbridge P-states */ /* Configure northbridge P-states */
dword = pci_read_config32(dev, 0xe0); dword = pci_read_config32(dev, 0x170);
dword &= ~(0x7 << 9); /* NbPstateThreshold = compute_unit_count */ dword &= ~(0x7 << 9); /* NbPstateThreshold = compute_unit_count */
dword |= (compute_unit_count & 0x7) << 9; dword |= (compute_unit_count & 0x7) << 9;
pci_write_config32(dev, 0xe0, dword); pci_write_config32(dev, 0x170, dword);
printk(BIOS_DEBUG, "done.\n"); printk(BIOS_DEBUG, "done.\n");
} }

21
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -1755,6 +1755,8 @@ static void detect_and_enable_probe_filter(device_t dev)
disable_cache(); disable_cache();
wbinvd(); wbinvd();
/* Enable probe filter */
for (i = 0; i < sysconf.nodes; i++) { for (i = 0; i < sysconf.nodes; i++) {
device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
@ -1771,6 +1773,25 @@ static void detect_and_enable_probe_filter(device_t dev)
do { do {
} while (!(pci_read_config32(f3x_dev, 0x1d4) & (0x1 << 19))); } while (!(pci_read_config32(f3x_dev, 0x1d4) & (0x1 << 19)));
} }
if (is_fam15h()) {
printk(BIOS_DEBUG, "Enabling ATM mode\n");
/* Enable ATM mode */
for (i = 0; i < sysconf.nodes; i++) {
device_t f0x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 0));
device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3));
dword = pci_read_config32(f0x_dev, 0x68);
dword |= (0x1 << 12); /* ATMModeEn = 1 */
pci_write_config32(f0x_dev, 0x68, dword);
dword = pci_read_config32(f3x_dev, 0x1b8);
dword |= (0x1 << 27); /* L3ATMModeEn = 1 */
pci_write_config32(f3x_dev, 0x1b8, dword);
}
}
enable_cache(); enable_cache();
/* Reenable L3 and DRAM scrubbers */ /* Reenable L3 and DRAM scrubbers */