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soc/intel/skylake: reduce postcar stack usage for fsp 2.0 

The FSP 2.0 path uses postcar to decompress ramstage. Since postcar
is entirely RAM based there's no need to have an excessively large
stack for the lzma decompression buffer. Therefore, reduce the stack
required to 1 KiB like apollolake.

Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2017-07-11 17:29:02 -06:00 committed by Aaron Durbin
parent ce9c88348c
commit 4dc9fb026c
1 changed files with 1 additions and 7 deletions
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8
src/soc/intel/skylake/romstage/romstage_fsp20.c
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@ -36,12 +36,6 @@
#include <timestamp.h> #include <timestamp.h>
#include <vboot/vboot_common.h> #include <vboot/vboot_common.h>
/*
* Romstage needs some stack for decompressing ramstage images, since the lzma
* lib keeps its state on the stack during romstage.
*/
#define ROMSTAGE_RAM_STACK_SIZE 0x5000
#define FSP_SMBIOS_MEMORY_INFO_GUID \ #define FSP_SMBIOS_MEMORY_INFO_GUID \
{ \ { \
0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \
@ -134,7 +128,7 @@ asmlinkage void car_stage_entry(void)
pmc_set_disb(); pmc_set_disb();
if (!s3wake) if (!s3wake)
save_dimm_info(); save_dimm_info();
if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) if (postcar_frame_init(&pcf, 1*KiB))
die("Unable to initialize postcar frame.\n"); die("Unable to initialize postcar frame.\n");
/* /*