intel/kblrvp: Move lockdown config to baseboard devicetree
Clean up lockdown configuration and move it to the baseboard's devicetree. Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it for the rvp8 variant for consistency as well. Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains identical. intel/rvp8 changes, as expected. Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -110,6 +110,10 @@ chip soc/intel/skylake
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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@ -105,11 +105,6 @@ chip soc/intel/skylake
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.tdp_pl2_override = 60,
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}"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device domain 0 on
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device pci 04.0 off end # SA thermal subsystem
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device pci 17.0 on end # SATA
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@ -110,11 +110,6 @@ chip soc/intel/skylake
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
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}"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device domain 0 on
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device pci 05.0 on end # SA IMGU
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device pci 14.3 on end # Camera
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@ -150,11 +150,6 @@ chip soc/intel/skylake
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# Use default SD card detect GPIO configuration
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register "sdcard_cd_gpio" = "GPP_G5"
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# Lock Down
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register "common_soc_config" = "{
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.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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