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mb/google/zork: Modify USB 2.0 PHY parameters for Woomax 

Modify USB 2.0 PHY parameters for improve usb eye diagram.
1. USB 2.0 TypeC port0:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,

2. USB 2.0 TypeC port3:
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,

BUG=b:169207729
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I764238485a1a81eb0d4740ac58c80a43f965f550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kane Chen 2020-09-23 11:18:06 +08:00 committed by Aaron Durbin
parent 1861ca4bb8
commit 4dcccc8365
1 changed files with 24 additions and 0 deletions
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24
src/mainboard/google/zork/variants/woomax/overridetree.cb
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@ -22,6 +22,30 @@ chip soc/amd/picasso
register "telemetry_vddcr_soc_offset" = "0"
# End : OPN Performance Configuration
#USB 2.0 strength
register "usb_2_port_tune_params[0]" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
register "usb_2_port_tune_params[3]" = "{
.com_pds_tune = 0x03,
.sq_rx_tune = 0x3,
.tx_fsls_tune = 0x3,
.tx_pre_emp_amp_tune = 0x03,
.tx_pre_emp_pulse_tune = 0x0,
.tx_rise_tune = 0x1,
.rx_vref_tune = 0xf,
.tx_hsxv_tune = 0x3,
.tx_res_tune = 0x01,
}"
# USB OC pin mapping
register "usb_port_overcurrent_pin[2]" = "USB_OC_NONE" # NC