soc/intel/quark: Add USB PHY initialization

Add register access support using register scripts.
Initialize the USB PHY using register scripts.

TEST=Build and run on Galileo Gen2

Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14496
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

src/soc/intel/quark/Kconfig

@@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
 	select ARCH_RAMSTAGE_X86_32
 	select ARCH_ROMSTAGE_X86_32
 	select ARCH_VERSTAGE_X86_32
+	select REG_SCRIPT
 	select SOC_INTEL_COMMON
 	select SOC_SETS_MTRRS
 	select TSC_CONSTANT_RATE

src/soc/intel/quark/Makefile.inc

@@ -19,6 +19,7 @@ subdirs-y += romstage
 subdirs-y += ../../../cpu/x86/tsc
 
 romstage-y += memmap.c
+romstage-y += reg_access.c
 romstage-y += tsc_freq.c
 romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
 
@@ -27,9 +28,11 @@ ramstage-y += chip.c
 ramstage-y += memmap.c
 ramstage-y += northcluster.c
 ramstage-y += pmc.c
+ramstage-y += reg_access.c
 ramstage-y += tsc_freq.c
 ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
 ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
+ramstage-y += usb.c
 
 CPPFLAGS_common += -I$(src)/soc/intel/quark
 CPPFLAGS_common += -I$(src)/soc/intel/quark/include

src/soc/intel/quark/include/soc/pci_devs.h

@@ -25,9 +25,11 @@
 /* DEVICE 0 (Memroy Controller Hub) */
 #define MC_BDF		PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN)
 
-/* IO Fabric 1 */
-#define HSUART_DEVID	0x0936
+/* Device IDs */
+#define HSUART_DEVID		0x0936
+#define EHCI_DEVID		0x0939
 
+/* IO Fabric 1 */
 #define SIO1_DEV 0x14
 # define HSUART1_DEV SIO1_DEV
 # define HSUART1_FUNC 5

src/soc/intel/quark/include/soc/reg_access.h

@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _QUARK_REG_ACCESS_H_
+#define _QUARK_REG_ACCESS_H_
+
+#include <fsp/util.h>
+#include <reg_script.h>
+#include <soc/QuarkNcSocId.h>
+
+enum {
+	USB_PHY_REGS = 1,
+};
+
+enum {
+	SOC_TYPE = REG_SCRIPT_TYPE_SOC_BASE,
+	/* Add additional SOC access types here*/
+};
+
+#define SOC_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_)   \
+	_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE,        \
+			       size_, reg_, mask_, value_, timeout_, reg_set_)
+#define REG_USB_ACCESS(cmd_, reg_, mask_, value_, timeout_) \
+	SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \
+		USB_PHY_REGS)
+#define REG_USB_READ(reg_) \
+	REG_USB_ACCESS(READ, reg_, 0, 0, 0)
+#define REG_USB_WRITE(reg_, value_) \
+	REG_USB_ACCESS(WRITE, reg_, 0, value_, 0)
+#define REG_USB_AND(reg_, value_) \
+	REG_USB_RMW(reg_, value_, 0)
+#define REG_USB_RMW(reg_, mask_, value_) \
+	REG_USB_ACCESS(RMW, reg_, mask_, value_, 0)
+#define REG_USB_RXW(reg_, mask_, value_) \
+	REG_USB_ACCESS(RXW, reg_, mask_, value_, 0)
+#define REG_USB_OR(reg_, value_) \
+	REG_USB_RMW(reg_, 0xffffffff, value_)
+#define REG_USB_POLL(reg_, mask_, value_, timeout_) \
+	REG_USB_ACCESS(POLL, reg_, mask_, value_, timeout_)
+#define REG_USB_XOR(reg_, value_) \
+	REG_USB_RXW(reg_, 0xffffffff, value_)
+
+void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
+uint32_t mdr_read(void);
+void mdr_write(uint32_t value);
+void mea_write(uint32_t reg_address);
+
+#endif /* _QUARK_REG_ACCESS_H_ */

src/soc/intel/quark/include/soc/romstage.h

@@ -23,13 +23,8 @@
 #endif
 
 #include <fsp/romstage.h>
-#include <fsp/util.h>
-#include <soc/QuarkNcSocId.h>
+#include <soc/reg_access.h>
 
-void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address);
-uint32_t mdr_read(void);
-void mdr_write(uint32_t value);
-void mea_write(uint32_t reg_address);
 uint32_t port_reg_read(uint8_t port, uint32_t offset);
 void port_reg_write(uint8_t port, uint32_t offset, uint32_t value);
 void report_platform_info(void);

src/soc/intel/quark/reg_access.c

@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#define __SIMPLE_DEVICE__
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <soc/pci_devs.h>
+#include <soc/reg_access.h>
+
+void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address)
+{
+	pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR,
+		(opcode << QNC_MCR_OP_OFFSET)
+		| ((uint32_t)port << QNC_MCR_PORT_OFFSET)
+		| ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET)
+		| QNC_MCR_BYTE_ENABLES);
+}
+
+uint32_t mdr_read(void)
+{
+	return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR);
+}
+
+void mdr_write(uint32_t value)
+{
+	pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value);
+}
+
+void mea_write(uint32_t reg_address)
+{
+	pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address
+		& QNC_MEA_MASK);
+}
+
+static uint32_t reg_usb_read(uint32_t reg_address)
+{
+	/* Read the USB register */
+	mea_write(reg_address);
+	mcr_write(QUARK_ALT_OPCODE_READ, QUARK_SC_USB_AFE_SB_PORT_ID,
+		reg_address);
+	return mdr_read();
+}
+
+static void reg_usb_write(uint32_t reg_address, uint32_t value)
+{
+	/* Write the USB register */
+	mea_write(reg_address);
+	mdr_write(value);
+	mcr_write(QUARK_ALT_OPCODE_WRITE, QUARK_SC_USB_AFE_SB_PORT_ID,
+		reg_address);
+}
+
+static uint64_t reg_read(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = ctx->step;
+	uint64_t value = 0;
+
+	switch (step->id) {
+	default:
+		printk(BIOS_ERR,
+			"ERROR - Unknown register set (0x%08x)!\n",
+			step->id);
+		ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
+		return 0;
+
+	case USB_PHY_REGS:
+		ctx->display_prefix = "USB PHY";
+		value = reg_usb_read(step->reg);
+		break;
+	}
+	return value;
+}
+
+static void reg_write(struct reg_script_context *ctx)
+{
+	const struct reg_script *step = ctx->step;
+
+	switch (step->id) {
+	default:
+		printk(BIOS_ERR,
+			"ERROR - Unknown register set (0x%08x)!\n",
+			step->id);
+		ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
+		return;
+
+	case USB_PHY_REGS:
+		ctx->display_prefix = "USB PHY";
+		reg_usb_write(step->reg, (uint32_t)step->value);
+		break;
+	}
+}
+
+const struct reg_script_bus_entry soc_reg_script_bus_table = {
+	SOC_TYPE, reg_read, reg_write
+};
+
+REG_SCRIPT_BUS_ENTRY(soc_reg_script_bus_table);

src/soc/intel/quark/romstage/mtrr.c

@@ -21,31 +21,6 @@
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 
-void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address)
-{
-	pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR,
-		(opcode << QNC_MCR_OP_OFFSET)
-		| ((uint32_t)port << QNC_MCR_PORT_OFFSET)
-		| ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET)
-		| QNC_MCR_BYTE_ENABLES);
-}
-
-uint32_t mdr_read(void)
-{
-	return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR);
-}
-
-void mdr_write(uint32_t value)
-{
-	pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value);
-}
-
-void mea_write(uint32_t reg_address)
-{
-	pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address
-		& QNC_MEA_MASK);
-}
-
 static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index)
 {
 	uint32_t offset;

src/soc/intel/quark/usb.c

@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <soc/pci_devs.h>
+#include <soc/reg_access.h>
+
+/* USB Phy Registers */
+#define USB2_GLOBAL_PORT  0x4001
+#define USB2_PLL1         0x7F02
+#define USB2_PLL2         0x7F03
+#define USB2_COMPBG       0x7F04
+
+/* In order to configure the USB PHY to use clk120 (ickusbcoreclk) as PLL
+ * reference clock and Port2 as a USB device port, the following sequence must
+ * be followed
+ */
+static const struct reg_script init_script[] = {
+
+	/* Sighting #4930631 PDNRESCFG [8:7] of USB2_GLOBAL_PORT = 11b.
+	 * For port 0 & 1 as host and port 2 as device.
+	 */
+	REG_USB_RXW(USB2_GLOBAL_PORT, ~(BIT8 | BIT7 | BIT1), (BIT8 | BIT7)),
+
+	/*
+	 * Sighting #4930653 Required BIOS change on Disconnect vref to change
+	 * to 600mV.
+	 */
+	REG_USB_RXW(USB2_COMPBG, ~(BIT10 | BIT9 | BIT8 | BIT7),
+		(BIT10 | BIT7)),
+
+	/* Sideband register write to USB AFE (Phy)
+	 * (pllbypass) to bypass/Disable PLL before switch
+	 */
+	REG_USB_OR(USB2_PLL2, BIT29),
+
+	/* Sideband register write to USB AFE (Phy)
+	 * (coreclksel) to select 120MHz (ickusbcoreclk) clk source.
+	 * (Default 0 to select 96MHz (ickusbclk96_npad/ppad))
+	 */
+	REG_USB_OR(USB2_PLL1, BIT1),
+
+	/* Sideband register write to USB AFE (Phy)
+	 * (divide by 8) to achieve internal 480MHz clock
+	 * for 120MHz input refclk.  (Default: 4'b1000 (divide by 10) for 96MHz)
+	 */
+	REG_USB_RXW(USB2_PLL1, ~(BIT6 | BIT5 | BIT4 | BIT3), BIT6),
+
+	/* Sideband register write to USB AFE (Phy)
+	 * Clear (pllbypass)
+	 */
+	REG_USB_AND(USB2_PLL2, ~BIT29),
+
+	/* Sideband register write to USB AFE (Phy)
+	 * Set (startlock) to force the PLL FSM to restart the lock
+	 * sequence due to input clock/freq switch.
+	 */
+	REG_USB_OR(USB2_PLL2, BIT24),
+	REG_SCRIPT_END
+};
+
+static void init(device_t dev)
+{
+	printk(BIOS_INFO, "Initializing USB PLLs\n");
+	reg_script_run_on_dev(dev, init_script);
+}
+
+static struct device_operations device_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= init,
+};
+
+static const struct pci_driver driver __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= EHCI_DEVID,
+};