sb/intel/bd82x6x: Make me_common.c a compilation unit
We need to make most things non-static so that the code builds. Also, we need to update ibexpeak as well, because it borrows files from bd82x6x. Tested on Asus P8Z77-V LX2, still boots. Change-Id: I17e561abf2378632f72d0aa9f0057cb1bee23514 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42019 Reviewed-by: Evgeny Zinoviev <me@ch1p.io> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
parent
3fe1ad1f26
commit
4def30d550
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@ -16,6 +16,7 @@ ramstage-y += usb_ehci.c
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ramstage-y += usb_xhci.c
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ramstage-y += me.c
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ramstage-y += me_8.x.c
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ramstage-y += me_common.c
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ramstage-y += smbus.c
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ramstage-y += ../common/pciehp.c
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@ -25,7 +26,7 @@ ramstage-y += me_status.c
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ramstage-$(CONFIG_ELOG) += elog.c
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smm-y += smihandler.c me.c me_8.x.c pch.c
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smm-y += smihandler.c me.c me_8.x.c pch.c me_common.c
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romstage-y += me_status.c
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romstage-y += early_rcba.c
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@ -27,9 +27,6 @@
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#include <vendorcode/google/chromeos/gnvs.h>
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#endif
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/* FIXME: For verification purposes only */
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#include "me_common.c"
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/* Send END OF POST message to the ME */
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static int __unused mkhi_end_of_post(void)
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{
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@ -220,6 +220,33 @@ typedef enum {
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ME_FIRMWARE_UPDATE_BIOS_PATH,
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} me_bios_path;
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/* Defined in me_common.c for both ramstage and smm */
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const char *const me_get_bios_path_string(int path);
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void mei_read_dword_ptr(void *ptr, int offset);
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void mei_write_dword_ptr(void *ptr, int offset);
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#ifndef __SIMPLE_DEVICE__
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void pci_read_dword_ptr(struct device *dev, void *ptr, int offset);
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#endif
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void read_host_csr(struct mei_csr *csr);
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void write_host_csr(struct mei_csr *csr);
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void read_me_csr(struct mei_csr *csr);
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void write_cb(u32 dword);
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u32 read_cb(void);
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int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
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void *req_data, void *rsp_data, int rsp_bytes);
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void update_mei_base_address(void);
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bool is_mei_base_address_valid(void);
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int intel_mei_setup(struct device *dev);
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int intel_me_extend_valid(struct device *dev);
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void intel_me_hide(struct device *dev);
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/* Defined in me_status.c for both romstage and ramstage */
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void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
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@ -27,9 +27,6 @@
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#include <vendorcode/google/chromeos/gnvs.h>
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#endif
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/* FIXME: For verification purposes only */
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#include "me_common.c"
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/* Send END OF POST message to the ME */
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static int __unused mkhi_end_of_post(void)
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{
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@ -16,7 +16,7 @@
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#include "pch.h"
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/* Path that the BIOS should take based on ME state */
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static const char *me_bios_path_values[] __unused = {
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static const char *const me_bios_path_values[] = {
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[ME_NORMAL_BIOS_PATH] = "Normal",
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[ME_S3WAKE_BIOS_PATH] = "S3 Wake",
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[ME_ERROR_BIOS_PATH] = "Error",
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@ -25,7 +25,7 @@ static const char *me_bios_path_values[] __unused = {
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[ME_FIRMWARE_UPDATE_BIOS_PATH] = "Firmware Update",
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};
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static inline const char *const me_get_bios_path_string(int path)
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const char *const me_get_bios_path_string(int path)
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{
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return me_bios_path_values[path];
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}
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@ -70,14 +70,14 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
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* ME/MEI access helpers using memcpy to avoid aliasing.
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*/
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static inline void mei_read_dword_ptr(void *ptr, int offset)
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void mei_read_dword_ptr(void *ptr, int offset)
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{
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u32 dword = read32(mei_base_address + (offset / sizeof(u32)));
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memcpy(ptr, &dword, sizeof(dword));
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mei_dump(ptr, dword, offset, "READ");
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}
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static inline void mei_write_dword_ptr(void *ptr, int offset)
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void mei_write_dword_ptr(void *ptr, int offset)
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{
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u32 dword = 0;
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memcpy(&dword, ptr, sizeof(dword));
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@ -86,7 +86,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
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}
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#ifndef __SIMPLE_DEVICE__
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static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
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void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
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{
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u32 dword = pci_read_config32(dev, offset);
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memcpy(ptr, &dword, sizeof(dword));
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@ -94,28 +94,28 @@ static inline void pci_read_dword_ptr(struct device *dev, void *ptr, int offset)
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}
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#endif
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static inline void read_host_csr(struct mei_csr *csr)
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void read_host_csr(struct mei_csr *csr)
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{
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mei_read_dword_ptr(csr, MEI_H_CSR);
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}
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static inline void write_host_csr(struct mei_csr *csr)
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void write_host_csr(struct mei_csr *csr)
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{
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mei_write_dword_ptr(csr, MEI_H_CSR);
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}
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static inline void read_me_csr(struct mei_csr *csr)
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void read_me_csr(struct mei_csr *csr)
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{
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mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
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}
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static inline void write_cb(u32 dword)
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void write_cb(u32 dword)
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{
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write32(mei_base_address + (MEI_H_CB_WW / sizeof(u32)), dword);
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mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
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}
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static inline u32 read_cb(void)
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u32 read_cb(void)
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{
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u32 dword = read32(mei_base_address + (MEI_ME_CB_RW / sizeof(u32)));
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mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
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@ -175,6 +175,7 @@ static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi, void *
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/* Pad non-dword aligned request message length */
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if (mei->length & 3)
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ndata++;
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if (!ndata) {
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printk(BIOS_DEBUG, "ME: request does not include MKHI\n");
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return -1;
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@ -250,6 +251,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes)
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break;
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udelay(ME_DELAY);
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}
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if (!n) {
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printk(BIOS_ERR, "ME: timeout waiting for data: expected %u, available %u\n",
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expected, me.buffer_write_ptr - me.buffer_read_ptr);
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@ -267,6 +269,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes)
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ndata = mei_rsp.length >> 2;
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if (mei_rsp.length & 3)
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ndata++;
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if (ndata != (expected - 1)) {
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printk(BIOS_ERR, "ME: response is missing data %d != %d\n",
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ndata, (expected - 1));
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@ -307,7 +310,7 @@ static int mei_recv_msg(struct mkhi_header *mkhi, void *rsp_data, int rsp_bytes)
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return mei_wait_for_me_ready();
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}
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static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
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int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
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void *req_data, void *rsp_data, int rsp_bytes)
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{
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if (mei_send_msg(mei, mkhi, req_data) < 0)
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@ -319,13 +322,13 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
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#ifdef __SIMPLE_DEVICE__
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static inline void update_mei_base_address(void)
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void update_mei_base_address(void)
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{
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uint32_t reg32 = pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
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mei_base_address = (u32 *)(uintptr_t)reg32;
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}
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static inline bool is_mei_base_address_valid(void)
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bool is_mei_base_address_valid(void)
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{
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return mei_base_address && mei_base_address != (u32 *)0xfffffff0;
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}
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@ -333,7 +336,7 @@ static inline bool is_mei_base_address_valid(void)
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#else
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/* Prepare ME for MEI messages */
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static int intel_mei_setup(struct device *dev)
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int intel_mei_setup(struct device *dev)
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{
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struct resource *res;
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struct mei_csr host;
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@ -364,7 +367,7 @@ static int intel_mei_setup(struct device *dev)
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#endif
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/* Read the Extend register hash of ME firmware */
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static int intel_me_extend_valid(struct device *dev)
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int intel_me_extend_valid(struct device *dev)
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{
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struct me_heres status;
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u32 extend[8] = {0};
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@ -411,7 +414,7 @@ static int intel_me_extend_valid(struct device *dev)
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}
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/* Hide the ME virtual PCI devices */
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static void intel_me_hide(struct device *dev)
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void intel_me_hide(struct device *dev)
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{
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dev->enabled = 0;
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pch_enable(dev);
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@ -14,6 +14,7 @@ ramstage-y += sata.c
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ramstage-y += usb_ehci.c
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ramstage-y += me.c
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ramstage-y += ../bd82x6x/me_8.x.c
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ramstage-y += ../bd82x6x/me_common.c
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ramstage-y += smbus.c
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ramstage-y += thermal.c
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ramstage-y += ../common/pciehp.c
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@ -25,7 +26,7 @@ ramstage-y += ../bd82x6x/me_status.c
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ramstage-$(CONFIG_ELOG) += ../bd82x6x/elog.c
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ramstage-y += madt.c
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smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c
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smm-y += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/me_common.c
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romstage-y += early_pch.c
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romstage-y +=../bd82x6x/early_me.c
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