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mb/intel/adlrvp_m: correct SSD power sequence 

This is to fix SSD detectiong failure in warm boot observed
on ADL-M RVP. This patch implements the coreect power sequence:
SSD_PREST Low - SSD_PWR_EN High - SSD_PREST High

Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: If6f9fc17a30c28c2948809cdbade9919d4ddd6c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
This commit is contained in:
Selma Bensaid 2021-09-21 15:57:51 -07:00 committed by Felix Held
parent 03aef28f16
commit 4df35b6ec8
2 changed files with 11 additions and 4 deletions
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11
src/mainboard/intel/adlrvp/early_gpio_m.c
View File

@ -12,6 +12,11 @@ static const struct pad_config early_gpio_table[] = {
/* WWAN_PWR_EN */
PAD_CFG_GPO(GPP_A8, 1, DEEP),
/* H0 : PCH_SSD_RST# */
PAD_CFG_GPO(GPP_H0, 0, PLTRST),
/* H13 : CPU_SSD_RST# */
PAD_CFG_GPO(GPP_H13, 0, PLTRST),
/* CPU PCIe VGPIO for RP0 */
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_0, NONE, DEEP, NF1),
PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_1, NONE, DEEP, NF1),
@ -111,6 +116,12 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
/* F12 : GSPI1_MOSI */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
/* D10 : PCH_SSD_PWR_EN */
PAD_CFG_GPO(GPP_D10, 1, PLTRST),
/* D16 : CPU_SSD_PWR_EN */
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
};
static const struct pad_config early_uart_gpio_table[] = {

4
src/mainboard/intel/adlrvp/gpio_m.c
View File

@ -90,12 +90,8 @@ static const struct pad_config gpio_table[] = {
/* D9 : WWAN_FCP_POWER_OFF_N */
PAD_CFG_GPO(GPP_D9, 1, PLTRST),
/* D10 : PCH_SSD_PWR_EN */
PAD_CFG_GPO(GPP_D10, 1, PLTRST),
/* H0 : PCH_SSD_RST# */
PAD_CFG_GPO(GPP_H0, 1, PLTRST),
/* D16 : CPU_SSD_PWR_EN */
PAD_CFG_GPO(GPP_D16, 1, PLTRST),
/* H13 : CPU_SSD_RST# */
PAD_CFG_GPO(GPP_H13, 1, PLTRST),