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mb/google/brya/acpi: Save/restore/clear some registers over GC6 

Nvidia recommends saving and restoring the LTR Enable bit in PCIe config
space for the PCIe root port before/after GC6 entry. Also the detectable
error bit should be cleared, as there may be errors expected during the
GC6 flow.

BUG=b:214581763
TEST=no more correctable errors after GC6 entry/exit

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I058ce1b3f17fb6cc59785a85efaf9ea0504cf2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This commit is contained in:
Tim Wawrzynczak 2022-08-16 14:25:56 -06:00 committed by Felix Held
parent afa72ee684
commit 4dfcd7acdc
2 changed files with 30 additions and 0 deletions
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5
src/mainboard/google/brya/acpi/peg.asl
View File

@ -6,9 +6,14 @@ External (\_SB.PCI0.PEG0.PEGP.NPOF, MethodObj)
OperationRegion (PCIC, PCI_Config, 0x00, 0x100) OperationRegion (PCIC, PCI_Config, 0x00, 0x100)
Field (PCIC, AnyAcc, NoLock, Preserve) Field (PCIC, AnyAcc, NoLock, Preserve)
{ {
Offset (0x4a),
CEDR, 1, /* Correctable Error Detected, RW/1C/V */
Offset (0x52), Offset (0x52),
, 13, , 13,
LASX, 1, /* Link Active Status */ LASX, 1, /* Link Active Status */
Offset (0x69),
, 2,
LREN, 1, /* LTR Enabled */
Offset (0xe0), Offset (0xe0),
, 7, , 7,
NCB7, 1, /* Scratch bit to save L2/3 state */ NCB7, 1, /* Scratch bit to save L2/3 state */

25
src/mainboard/google/brya/acpi/power.asl
View File

@ -1,5 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */ /* SPDX-License-Identifier: GPL-2.0-or-later */
#include <device/pci_ids.h>
External (\_SB.PCI0.PMC.IPCS, MethodObj) External (\_SB.PCI0.PMC.IPCS, MethodObj)
/* Voltage rail control signals */ /* Voltage rail control signals */
@ -70,6 +72,8 @@ Name (GCOT, 0)
#define PMC_RP_IDX (1 << 27) #define PMC_RP_IDX (1 << 27)
#define PMC_RP_ENABLE (1 << 27) #define PMC_RP_ENABLE (1 << 27)
#define PMC_RP_DISABLE 0x0 #define PMC_RP_DISABLE 0x0
/* Copy of LTR enable bit from PEG port */
Name (SLTR, 0)
/* Control the PCIe SRCCLK# for dGPU */ /* Control the PCIe SRCCLK# for dGPU */
Method (SRCC, 1, Serialized) Method (SRCC, 1, Serialized)
@ -94,6 +98,9 @@ Method (GC6I, 0, Serialized)
{ {
GC6E = GC6_STATE_TRANSITION GC6E = GC6_STATE_TRANSITION
/* Save the PEG port's LTR setting */
SLTR = LREN
/* Put PCIe link into L2/3 */ /* Put PCIe link into L2/3 */
\_SB.PCI0.PEG0.DL23 () \_SB.PCI0.PEG0.DL23 ()
@ -152,6 +159,24 @@ Method (GC6O, 0, Serialized)
\_SB.PCI0.PEG0.LD23 () \_SB.PCI0.PEG0.LD23 ()
Printf ("dGPU exited GC6") Printf ("dGPU exited GC6")
/* Wait for dGPU to reappear on the bus */
Local0 = 50
While (NVID != PCI_VID_NVIDIA)
{
Stall (100)
Local0--
If (Local0 == 0)
{
Break
}
}
/* Restore the PEG LTR enable bit */
LREN = SLTR
/* Clear recoverable errors detected bit */
CEDR = 1
GC6E = GC6_STATE_EXITED GC6E = GC6_STATE_EXITED
} }