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AMD Olive Hill: Change SB800 references to Yangtze 

Change-Id: I7f6f6ff444fda4bdf233db1383919772afe6b635
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3815
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
This commit is contained in:
Bruce Griffith 2013-07-07 02:04:16 -06:00
parent effc8d087d
commit 4e08a95d26
4 changed files with 44 additions and 44 deletions
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30
src/mainboard/amd/olivehill/get_bus_conf.c
View File

@ -30,8 +30,8 @@
* and acpi_tables busnum is default.
*/
u8 bus_isa;
u8 bus_sb800[3];
u32 apicid_sb800;
u8 bus_yangtze[3];
u32 apicid_yangtze;
/*
* Here you only need to set value in pci1234 for HT-IO that could be installed or not
@ -43,7 +43,7 @@ u32 pci1234x[] = {
};
u32 bus_type[256];
u32 sbdn_sb800;
u32 sbdn_yangtze;
static u32 get_bus_conf_done = 0;
@ -98,10 +98,10 @@ void get_bus_conf(void)
pci_write_config32(dev, 0xF8, 0);
pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */
sbdn_sb800 = 0;
sbdn_yangtze = 0;
for (i = 0; i < 3; i++) {
bus_sb800[i] = 0;
bus_yangtze[i] = 0;
}
for (i = 0; i < 256; i++) {
@ -110,34 +110,34 @@ void get_bus_conf(void)
bus_type[0] = 1; /* pci */
// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb800[0] = (pci1234x[0] >> 16) & 0xff;
// bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff;
/* sb800 */
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4));
/* yangtze */
dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4));
if (dev) {
bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
for (j = bus_sb800[1]; j < bus_isa; j++)
for (j = bus_yangtze[1]; j < bus_isa; j++)
bus_type[j] = 1;
}
for (i = 0; i < 4; i++) {
dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i));
dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i));
if (dev) {
bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
}
}
for (j = bus_sb800[2]; j < bus_isa; j++)
for (j = bus_yangtze[2]; j < bus_isa; j++)
bus_type[j] = 1;
/* I/O APICs: APIC ID Version State Address */
bus_isa = 10;
apicid_base = CONFIG_MAX_CPUS;
apicid_sb800 = apicid_base;
apicid_yangtze = apicid_base;
}

10
src/mainboard/amd/olivehill/irq_tables.c
View File

@ -44,8 +44,8 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn,
}
extern u8 bus_isa;
extern u8 bus_sb800[2];
extern unsigned long sbdn_sb800;
extern u8 bus_yangtze[2];
extern unsigned long sbdn_yangtze;
unsigned long write_pirq_routing_table(unsigned long addr)
{
@ -72,8 +72,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq->signature = PIRQ_SIGNATURE;
pirq->version = PIRQ_VERSION;
pirq->rtr_bus = bus_sb800[0];
pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4;
pirq->rtr_bus = bus_yangtze[0];
pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4;
pirq->exclusive_irqs = 0;
@ -88,7 +88,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
slot_num = 0;
/* pci bridge */
write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4,
write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;

46
src/mainboard/amd/olivehill/mptable.c
View File

@ -30,11 +30,11 @@
//-#define IO_APIC_ID CONFIG_MAX_PHYSICAL_CPUS + 1
#define IO_APIC_ID CONFIG_MAX_CPUS
extern u8 bus_sb800[3];
extern u8 bus_yangtze[3];
extern u32 bus_type[256];
extern u32 sbdn_sb800;
extern u32 apicid_sb800;
extern u32 sbdn_yangtze;
extern u32 apicid_yangtze;
u8 picr_data[0x54] = {
0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
@ -103,10 +103,10 @@ static void *smp_write_config_table(void *v)
/* Set IO APIC ID onto IO_APIC_ID */
write32 (dword, 0x00);
write32 (dword + 0x10, IO_APIC_ID << 24);
apicid_sb800 = IO_APIC_ID;
smp_write_ioapic(mc, apicid_sb800, 0x21, dword);
apicid_yangtze = IO_APIC_ID;
smp_write_ioapic(mc, apicid_yangtze, 0x21, dword);
smp_write_ioapic(mc, apicid_sb800+1, 0x21, 0xFEC20000);
smp_write_ioapic(mc, apicid_yangtze+1, 0x21, 0xFEC20000);
/* PIC IRQ routine */
for (byte = 0x0; byte < sizeof(picr_data); byte ++) {
outb(byte, 0xC00);
@ -160,13 +160,13 @@ static void *smp_write_config_table(void *v)
/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
#define IO_LOCAL_INT(type, intr, apicid, pin) \
smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
mptable_add_isa_interrupts(mc, bus_isa, apicid_sb800, 0);
mptable_add_isa_interrupts(mc, bus_isa, apicid_yangtze, 0);
/* PCI interrupts are level triggered, and are
* associated with a specific bus/device/function tuple.
*/
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_yangtze, (pin))
/* Internal VGA */
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
@ -195,26 +195,26 @@ static void *smp_write_config_table(void *v)
/* PCI slots */
/* PCI_SLOT 0. */
PCI_INT(bus_sb800[1], 0x5, 0x0, 0x14);
PCI_INT(bus_sb800[1], 0x5, 0x1, 0x15);
PCI_INT(bus_sb800[1], 0x5, 0x2, 0x16);
PCI_INT(bus_sb800[1], 0x5, 0x3, 0x17);
PCI_INT(bus_yangtze[1], 0x5, 0x0, 0x14);
PCI_INT(bus_yangtze[1], 0x5, 0x1, 0x15);
PCI_INT(bus_yangtze[1], 0x5, 0x2, 0x16);
PCI_INT(bus_yangtze[1], 0x5, 0x3, 0x17);
/* PCI_SLOT 1. */
PCI_INT(bus_sb800[1], 0x6, 0x0, 0x15);
PCI_INT(bus_sb800[1], 0x6, 0x1, 0x16);
PCI_INT(bus_sb800[1], 0x6, 0x2, 0x17);
PCI_INT(bus_sb800[1], 0x6, 0x3, 0x14);
PCI_INT(bus_yangtze[1], 0x6, 0x0, 0x15);
PCI_INT(bus_yangtze[1], 0x6, 0x1, 0x16);
PCI_INT(bus_yangtze[1], 0x6, 0x2, 0x17);
PCI_INT(bus_yangtze[1], 0x6, 0x3, 0x14);
/* PCI_SLOT 2. */
PCI_INT(bus_sb800[1], 0x7, 0x0, 0x16);
PCI_INT(bus_sb800[1], 0x7, 0x1, 0x17);
PCI_INT(bus_sb800[1], 0x7, 0x2, 0x14);
PCI_INT(bus_sb800[1], 0x7, 0x3, 0x15);
PCI_INT(bus_yangtze[1], 0x7, 0x0, 0x16);
PCI_INT(bus_yangtze[1], 0x7, 0x1, 0x17);
PCI_INT(bus_yangtze[1], 0x7, 0x2, 0x14);
PCI_INT(bus_yangtze[1], 0x7, 0x3, 0x15);
PCI_INT(bus_sb800[2], 0x0, 0x0, 0x12);
PCI_INT(bus_sb800[2], 0x0, 0x1, 0x13);
PCI_INT(bus_sb800[2], 0x0, 0x2, 0x14);
PCI_INT(bus_yangtze[2], 0x0, 0x0, 0x12);
PCI_INT(bus_yangtze[2], 0x0, 0x1, 0x13);
PCI_INT(bus_yangtze[2], 0x0, 0x2, 0x14);
/* PCIe Lan*/
PCI_INT(0x0, 0x06, 0x0, 0x13);

2
src/mainboard/amd/olivehill/romstage.c
View File

@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
post_code(0x38);
printk(BIOS_DEBUG, "Got past sb800_early_setup\n");
printk(BIOS_DEBUG, "Got past yangtze_early_setup\n");
post_code(0x39);