mb/google/poppy/variants/nami: Add gpio-keys ACPI node for PENH
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:73121017 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I5d87d938ac3a4e52e676850b9d8b80e83726275d Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -279,9 +279,19 @@ chip soc/intel/skylake
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register "generic.reset_delay_ms" = "20"
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register "generic.has_power_resource" = "1"
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register "generic.disable_gpio_export_in_crs" = "1"
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register "generic.wake" = "GPE0_DW2_01"
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register "hid_desc_reg_offset" = "0x1"
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device i2c 0x9 on end
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end
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chip drivers/generic/gpio_keys
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register "name" = ""PENH""
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register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_E8)"
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register "key.dev_name" = ""EJCT""
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register "key.linux_code" = "SW_PEN_INSERTED"
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register "key.linux_input_type" = "EV_SW"
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register "key.label" = ""pen_eject""
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device generic 0 on end
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end
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end # I2C #2
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device pci 15.3 on
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chip drivers/generic/max98357a
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@ -211,8 +211,8 @@ static const struct pad_config gpio_table[] = {
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/* E0 : SATAXPCI0 ==> H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST),
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/* E1 : SATAXPCIE1 ==> SATA_GP1 */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
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/* E1 : SATAXPCIE1 ==> PEN_EJECT_ODL - for wake event */
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PAD_CFG_GPI_ACPI_SCI(GPP_E1, NONE, DEEP, NONE),
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/* E2 : SATAXPCIE2 ==> NC(TP916) */
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PAD_CFG_NC(GPP_E2),
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/* E3 : CPU_GP0 ==> TRACKPAD_INT# */
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@ -225,8 +225,8 @@ static const struct pad_config gpio_table[] = {
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PAD_CFG_NC(GPP_E6),
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/* E7 : CPU_GP1 ==> TOUCHSCREEN_INT# */
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PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
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/* E8 : SATALED# ==> NC */
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PAD_CFG_NC(GPP_E8),
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/* E8 : SATALED# ==> PEN_EJECT_ODL - for notification */
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PAD_CFG_GPI_GPIO_DRIVER(GPP_E8, NONE, DEEP),
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/* E9 : USB2_OCO# ==> USB_C0_OC# */
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
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/* E10 : USB2_OC1# ==> USB_C1_OC# */
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