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{drivers,soc/intel/braswell}: Implement C_ENVIRONMENT_BOOTBLOCK support 

No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.

The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()

Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()

BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
     Building Google Banos

Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Frans Hendriks 2019-06-06 10:07:17 +02:00 committed by Arthur Heymans
parent ba50e4885f
commit 4e0ec59255
15 changed files with 138 additions and 195 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/drivers/intel/fsp1_1/Makefile.inc
View File

@ -21,6 +21,7 @@ verstage-y += fsp_util.c
verstage-$(CONFIG_SEPARATE_VERSTAGE) += verstage.c
bootblock-y += bootblock.c
bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S
bootblock-y += fsp_util.c
romstage-y += car.c
@ -42,8 +43,6 @@ ramstage-$(CONFIG_MMA) += mma_core.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include
cpu_incs-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += $(src)/drivers/intel/fsp1_1/cache_as_ram.inc
postcar-y += stage_cache.c
ifneq ($(CONFIG_SKIP_FSP_CAR),y)
postcar-y += temp_ram_exit.c

22
src/drivers/intel/fsp1_1/cache_as_ram.inc → src/drivers/intel/fsp1_1/cache_as_ram.S
View File

@ -5,6 +5,7 @@
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2018-2019 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -16,6 +17,8 @@
* GNU General Public License for more details.
*/
#include <cpu/x86/post_code.h>
/*
* Replacement for cache_as_ram.inc when using the FSP binary. This code
* locates the FSP binary, initializes the cache as RAM and performs the
@ -24,8 +27,10 @@
* performs the final stage of initialization.
*/
/* I/O delay between post codes on failure */
#define LHLT_DELAY 0x50000
#define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */
.global bootblock_pre_c_entry
bootblock_pre_c_entry:
/*
* Per FSP1.1 specs, following registers are preserved:
* EBX, EDI, ESI, EBP, MM0, MM1
@ -129,10 +134,9 @@ CAR_init_done:
/* Need to align stack to 16 bytes at call instruction. Account for
the pushes below. */
andl $0xfffffff0, %esp
subl $4, %esp
subl $8, %esp
/* Push BIST and initial timestamp on the stack */
pushl %ebx /* bist */
/* Push initial timestamp on the stack */
movd %mm1, %eax
pushl %eax /* tsc[63:32] */
movd %mm0, %eax
@ -141,12 +145,10 @@ CAR_init_done:
before_romstage:
post_code(0x2A)
/* Call bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
in cpu/intel/car/romstage.c */
call bootblock_c_entry_bist
/* Call bootblock_c_entry(uint64_t base_timestamp) */
call bootblock_c_entry
movb $0x69, %ah
jmp .Lhlt
/* Never reached */
halt1:
/*

28
src/drivers/intel/fsp1_1/car.c
View File

@ -101,18 +101,6 @@ void mainboard_romstage_entry(unsigned long bist)
* is still enabled. We can directly access work buffer here. */
struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin");
if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) {
/* Call into pre-console init code then initialize console. */
car_soc_pre_console_init();
car_mainboard_pre_console_init();
console_init();
display_mtrrs();
car_soc_post_console_init();
car_mainboard_post_console_init();
}
if (prog_locate(&fsp))
die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin");
@ -125,19 +113,3 @@ void mainboard_romstage_entry(unsigned long bist)
cache_as_ram_stage_main(fih);
}
void __weak car_mainboard_pre_console_init(void)
{
}
void __weak car_soc_pre_console_init(void)
{
}
void __weak car_mainboard_post_console_init(void)
{
}
void __weak car_soc_post_console_init(void)
{
}

8
src/drivers/intel/fsp1_1/include/fsp/car.h
View File

@ -24,12 +24,4 @@
* cache_as_ram_stage_main() is the stack pointer to use in RAM after
* exiting cache-as-ram mode. */
void cache_as_ram_stage_main(FSP_INFO_HEADER *fih);
/* Mainboard and SoC initialization prior to console. */
void car_mainboard_pre_console_init(void);
void car_soc_pre_console_init(void);
/* Mainboard and SoC initialization post console initialization. */
void car_mainboard_post_console_init(void);
void car_soc_post_console_init(void);
#endif

3
src/mainboard/google/cyan/Makefile.inc
View File

@ -14,8 +14,9 @@
## GNU General Public License for more details.
##
bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
romstage-y += spd/spd.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c

4
src/mainboard/google/cyan/com_init.c
View File

@ -14,14 +14,14 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <soc/gpio.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
void car_mainboard_pre_console_init(void)
void bootblock_mainboard_early_init(void)
{
uint32_t reg;
uint32_t *pad_config_reg;

3
src/mainboard/intel/strago/Makefile.inc
View File

@ -14,8 +14,9 @@
## GNU General Public License for more details.
##
bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c
ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c

4
src/mainboard/intel/strago/com_init.c
View File

@ -14,12 +14,12 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <soc/gpio.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
/*
* return family number and internal pad number in that community
@ -30,7 +30,7 @@
/* family number in high byte and inner pad number in lowest byte */
void car_mainboard_pre_console_init(void)
void bootblock_mainboard_early_init(void)
{
uint32_t reg;
uint32_t *pad_config_reg;

16
src/soc/intel/braswell/Kconfig
View File

@ -51,15 +51,23 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_GMA_SWSMISCI
select CPU_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select C_ENVIRONMENT_BOOTBLOCK
config DCACHE_BSP_STACK_SIZE
hex
default 0x2000
help
The amount of anticipated stack usage in CAR by bootblock and
other stages.
config C_ENV_BOOTBLOCK_SIZE
hex
default 0x8000
config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE
config BOOTBLOCK_CPU_INIT
string
default "soc/intel/braswell/bootblock/bootblock.c"
config MMCONF_BASE_ADDRESS
hex
default 0xe0000000

7
src/soc/intel/braswell/Makefile.inc
View File

@ -9,9 +9,14 @@ subdirs-y += ../../../cpu/intel/microcode
subdirs-y += ../../../cpu/intel/turbo
subdirs-y += ../../../cpu/intel/common
bootblock-y += gpio_support.c
bootblock-y += bootblock/bootblock.c
bootblock-y += lpc_init.c
bootblock-y += pmutil.c
bootblock-y += tsc_freq.c
romstage-y += gpio_support.c
romstage-y += iosf.c
romstage-y += lpc_init.c
romstage-y += memmap.c
romstage-y += pmutil.c
romstage-y += smbus.c

119
src/soc/intel/braswell/bootblock/bootblock.c
View File

@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Google, Inc.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2018 Eltan B.V.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -14,37 +15,93 @@
* GNU General Public License for more details.
*/
#include <bootblock_common.h>
#include <build.h>
#include <console/console.h>
#include <device/pci_ops.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <pc80/mc146818rtc.h>
#include <soc/bootblock.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <cpu/intel/microcode/microcode.c>
#include <soc/lpc.h>
#include <soc/pm.h>
#include <soc/spi.h>
static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
{
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(reg), maskm);
/* Call lib/bootblock.c main */
bootblock_main_with_timestamp(base_timestamp, NULL, 0);
}
static void enable_rom_caching(void)
static void program_base_addresses(void)
{
msr_t msr;
uint32_t reg;
const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
disable_cache();
/* Why only top 4MiB ? */
set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
enable_cache();
/* Memory Mapped IO registers. */
reg = PMC_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, PBASE, reg);
reg = IO_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, IOBASE, reg);
reg = ILB_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, IBASE, reg);
reg = SPI_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, SBASE, reg);
reg = MPHY_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, MPBASE, reg);
reg = PUNIT_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, PUBASE, reg);
reg = RCBA_BASE_ADDRESS | 1;
pci_write_config32(lpc_dev, RCBA, reg);
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRR_DEF_TYPE_MSR, msr);
/* IO Port Registers. */
reg = ACPI_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, ABASE, reg);
reg = GPIO_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, GBASE, reg);
}
static void tco_disable(void)
{
uint32_t reg;
reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
reg |= TCO_TMR_HALT;
outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
}
static void spi_init(void)
{
void *scs = (void *)(SPI_BASE_ADDRESS + SCS);
void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
write32(scs, read32(scs) & ~SMIWPEN);
/*
* Enable caching and prefetching in the SPI controller. Disable
* the SMM-only BIOS write and set WPD bit.
*/
reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
reg &= ~EISS;
write32(bcr, reg);
}
static void soc_rtc_init(void)
{
int rtc_failed = rtc_failure();
if (rtc_failed) {
printk(BIOS_ERR,
"RTC Failure detected. Resetting date to %x/%x/%x%x\n",
COREBOOT_BUILD_MONTH_BCD,
COREBOOT_BUILD_DAY_BCD,
0x20,
COREBOOT_BUILD_YEAR_BCD);
}
cmos_init(rtc_failed);
}
static void setup_mmconfig(void)
@ -67,12 +124,22 @@ static void setup_mmconfig(void)
pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg);
}
static void bootblock_cpu_init(void)
void bootblock_soc_early_init(void)
{
/* Allow memory-mapped PCI config access. */
setup_mmconfig();
/* Load microcode before any caching. */
intel_update_microcode_from_cbfs();
enable_rom_caching();
/* Early chipset initialization */
program_base_addresses();
tco_disable();
}
void bootblock_soc_init(void)
{
/* Continue chipset initialization */
soc_rtc_init();
set_max_freq();
spi_init();
lpc_init();
}

16
src/soc/intel/braswell/romstage/pmc.c → src/soc/intel/braswell/include/soc/bootblock.h
View File

@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Google Inc.
* Copyright (C) 2015 Intel Corp.
* Copyright (C) 2015-2016 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -14,15 +14,9 @@
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <soc/iomap.h>
#include <soc/romstage.h>
#ifndef _SOC_BOOTBLOCK_H_
#define _SOC_BOOTBLOCK_H_
void tco_disable(void)
{
uint32_t reg;
void set_max_freq(void);
reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT);
reg |= TCO_TMR_HALT;
outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT);
}
#endif /* _SOC_BOOTBLOCK_H_ */

4
src/soc/intel/braswell/include/soc/romstage.h
View File

@ -23,12 +23,10 @@
#include <soc/pm.h>
void gfx_init(void);
void tco_disable(void);
void punit_init(void);
void set_max_freq(void);
/* romstage_common.c functions */
void program_base_addresses(void);
/* romstage.c functions */
int chipset_prev_sleep_state(struct chipset_power_state *ps);
/* Values for FSP's PcdMemoryTypeEnable */

1
src/soc/intel/braswell/romstage/Makefile.inc
View File

@ -1,3 +1,2 @@
romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += pmc.c
romstage-y += romstage.c

95
src/soc/intel/braswell/romstage/romstage.c
View File

@ -19,90 +19,13 @@
#include <stddef.h>
#include <arch/io.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
#include <arch/cbfs.h>
#include <cpu/x86/mtrr.h>
#include <console/console.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <elog.h>
#include <mrc_cache.h>
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <fsp/util.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
#include <soc/iosf.h>
#include <soc/lpc.h>
#include <soc/pci_devs.h>
#include <soc/romstage.h>
#include <soc/smm.h>
#include <soc/spi.h>
#include <build.h>
#include <pc80/mc146818rtc.h>
#include "../chip.h"
void program_base_addresses(void)
{
uint32_t reg;
const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC);
/* Memory Mapped IO registers. */
reg = PMC_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, PBASE, reg);
reg = IO_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, IOBASE, reg);
reg = ILB_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, IBASE, reg);
reg = SPI_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, SBASE, reg);
reg = MPHY_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, MPBASE, reg);
reg = PUNIT_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, PUBASE, reg);
reg = RCBA_BASE_ADDRESS | 1;
pci_write_config32(lpc_dev, RCBA, reg);
/* IO Port Registers. */
reg = ACPI_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, ABASE, reg);
reg = GPIO_BASE_ADDRESS | 2;
pci_write_config32(lpc_dev, GBASE, reg);
}
static void spi_init(void)
{
void *scs = (void *)(SPI_BASE_ADDRESS + SCS);
void *bcr = (void *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
write32(scs, read32(scs) & ~SMIWPEN);
/*
* Enable caching and prefetching in the SPI controller. Disable
* the SMM-only BIOS write and set WPD bit.
*/
reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD;
reg &= ~EISS;
write32(bcr, reg);
}
static void soc_rtc_init(void)
{
int rtc_failed = rtc_failure();
if (rtc_failed) {
printk(BIOS_ERR,
"RTC Failure detected. Resetting date to %x/%x/%x%x\n",
COREBOOT_BUILD_MONTH_BCD,
COREBOOT_BUILD_DAY_BCD,
0x20,
COREBOOT_BUILD_YEAR_BCD);
}
cmos_init(rtc_failed);
}
static struct chipset_power_state power_state;
@ -171,24 +94,6 @@ int chipset_prev_sleep_state(struct chipset_power_state *ps)
return prev_sleep_state;
}
/* SOC initialization before the console is enabled */
void car_soc_pre_console_init(void)
{
/* Early chipset initialization */
program_base_addresses();
tco_disable();
}
/* SOC initialization after console is enabled */
void car_soc_post_console_init(void)
{
/* Continue chipset initialization */
soc_rtc_init();
set_max_freq();
spi_init();
lpc_init();
}
/* SOC initialization after RAM is enabled */
void soc_after_ram_init(struct romstage_params *params)