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blaze: Create a nyan_blaze mainboard, copied from nyan_big 

The nyan_blaze board will have different BCT .inc files, to be
added/updated later. GPIOs and some devicetree stuff may also differ.

BUG=None
TEST=Built nyan, nyan_big and nyan_blaze.
BRANCH=None

Original-Change-Id: I8b16fc71346cf973983aa046096b79cb83ad4bb6
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/190721
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit bea753131e2247a90cc5359fa5f603026d66c7ce)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I435ae78da2f6c4f1a78fea8300b6285e52272535
Reviewed-on: http://review.coreboot.org/7453
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Tom Warren 2014-03-19 14:19:09 -07:00 committed by Marc Jones
parent 764cd1bb3a
commit 4e16a2ea17
24 changed files with 2829 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/Kconfig
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@ -35,6 +35,8 @@ config BOARD_GOOGLE_NYAN
bool "Nyan"
config BOARD_GOOGLE_NYAN_BIG
bool "Nyan Big"
config BOARD_GOOGLE_NYAN_BLAZE
bool "Nyan Blaze"
config BOARD_GOOGLE_PANTHER
bool "Panther"
config BOARD_GOOGLE_PARROT
@ -63,6 +65,7 @@ source "src/mainboard/google/falco/Kconfig"
source "src/mainboard/google/link/Kconfig"
source "src/mainboard/google/nyan/Kconfig"
source "src/mainboard/google/nyan_big/Kconfig"
source "src/mainboard/google/nyan_blaze/Kconfig"
source "src/mainboard/google/panther/Kconfig"
source "src/mainboard/google/parrot/Kconfig"
source "src/mainboard/google/peach_pit/Kconfig"

91
src/mainboard/google/nyan_blaze/Kconfig Normal file
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@ -0,0 +1,91 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
if BOARD_GOOGLE_NYAN_BLAZE
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select ARCH_ARM
select CHROMEOS
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
select SOC_NVIDIA_TEGRA124
select TEGRA124_MODEL_CD570M
select MAINBOARD_HAS_BOOTBLOCK_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
select BOARD_ROMSIZE_KB_1024
select SPI_FLASH
select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B
config MAINBOARD_DIR
string
default google/nyan_blaze
config MAINBOARD_PART_NUMBER
string
default "Nyan Blaze"
config DRAM_DMA_START
hex
default 0x90000000
config DRAM_DMA_SIZE
hex
default 0x00200000
choice
prompt "BCT boot media"
default NYAN_BLAZE_BCT_CFG_SPI
help
Which boot media to configure the BCT for.
config NYAN_BLAZE_BCT_CFG_SPI
bool "SPI"
help
Configure the BCT for booting from SPI.
config NYAN_BLAZE_BCT_CFG_EMMC
bool "eMMC"
help
Configure the BCT for booting from eMMC.
endchoice
config BOOT_MEDIA_SPI_BUS
int "SPI bus with boot media ROM"
range 1 6
depends on NYAN_BLAZE_BCT_CFG_SPI
default 4
help
Which SPI bus the boot media is connected to.
config BOOT_MEDIA_SPI_CHIP_SELECT
int "Chip select for SPI boot media"
range 0 3
depends on NYAN_BLAZE_BCT_CFG_SPI
default 0
help
Which chip select to use for boot media.
config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 1
endif # BOARD_GOOGLE_NYAN_BLAZE

39
src/mainboard/google/nyan_blaze/Makefile.inc Normal file
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@ -0,0 +1,39 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
# Add a handler for BCT config files
$(call add-special-class,bct-cfg)
bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2))
$(obj)/generated/bct.cfg:
@printf " CAT $(subst $(obj)/,,$(@))\n"
cat $^ > $@
subdirs-y += bct
bootblock-y += boardid.c
bootblock-y += bootblock.c
bootblock-y += pmic.c
romstage-y += romstage.c
romstage-y += sdram_configs.c
romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-y += mainboard.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c

26
src/mainboard/google/nyan_blaze/bct/Makefile.inc Normal file
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@ -0,0 +1,26 @@
##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
bct-cfg-$(CONFIG_NYAN_BLAZE_BCT_CFG_EMMC) += emmc.cfg
bct-cfg-$(CONFIG_NYAN_BLAZE_BCT_CFG_SPI) += spi.cfg
bct-cfg-y += odmdata.cfg
# Note when SDRAM config (sdram-*.cfg) files are changed, we have to regenerate
# the include files (sdram-*.inc). See ../../nyan/bct/Makefile.inc for more
# information.

13
src/mainboard/google/nyan_blaze/bct/emmc.cfg Normal file
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@ -0,0 +1,13 @@
# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
# Distributed under the terms of the GNU General Public License v2
Version = 0x00350001;
BlockSize = 0x00004000;
PageSize = 0x00000200;
PartitionSize = 0x01000000;
DevType[0] = NvBootDevType_Sdmmc;
DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009;
DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit;
DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000;
DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000;

1
src/mainboard/google/nyan_blaze/bct/odmdata.cfg Normal file
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@ -0,0 +1 @@
OdmData = 0x80080000;

311
src/mainboard/google/nyan_blaze/bct/sdram-hynix-2GB-204.inc Normal file
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@ -0,0 +1,311 @@
{ /* generated from sdram-0001-204-2GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x00000022,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x40000002,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000000,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000009,
.EmcRfc = 0x00000035,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x00000007,
.EmcRp = 0x00000002,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000005,
.EmcW2r = 0x0000000a,
.EmcR2p = 0x00000003,
.EmcW2p = 0x0000000b,
.EmcRdRcd = 0x00000002,
.EmcWrRcd = 0x00000002,
.EmcRrd = 0x00000003,
.EmcRext = 0x00000003,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000005,
.EmcWdvMask = 0x00000005,
.EmcQUse = 0x00000006,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000004,
.EmcEInputDuration = 0x00000006,
.EmcPutermExtra = 0x00010000,
.EmcPutermWidth = 0x00000003,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000003,
.EmcQSafe = 0x0000000d,
.EmcRdv = 0x0000000f,
.EmcRdvMask = 0x00000011,
.EmcQpop = 0x0000000a,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000003,
.EmcRefresh = 0x00000607,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x00000181,
.EmcPdEx2Wr = 0x00000002,
.EmcPdEx2Rd = 0x00000002,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x00000032,
.EmcRw2Pden = 0x0000000f,
.EmcTxsr = 0x00000038,
.EmcTxsrDll = 0x00000038,
.EmcTcke = 0x00000004,
.EmcTckesr = 0x00000005,
.EmcTpd = 0x00000004,
.EmcTfaw = 0x00000007,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x00000005,
.EmcTClkStop = 0x00000005,
.EmcTRefBw = 0x00000638,
.EmcFbioCfg5 = 0x106aa298,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x80001221,
.EmcEmrs = 0x80100003,
.EmcEmrs2 = 0x80200008,
.EmcEmrs3 = 0x80300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x000c000c,
.EmcMrsWaitCnt2 = 0x000c000c,
.EmcCfg = 0x73240000,
.EmcCfg2 = 0x0000088d,
.EmcCfgPipe = 0x0000d2b3,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80000d22,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0x002c00a0,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000002,
.EmcSelDpdCtrl = 0x00040008,
.EmcDllXformDqs0 = 0x00064000,
.EmcDllXformDqs1 = 0x00064000,
.EmcDllXformDqs2 = 0x00064000,
.EmcDllXformDqs3 = 0x00064000,
.EmcDllXformDqs4 = 0x00064000,
.EmcDllXformDqs5 = 0x00064000,
.EmcDllXformDqs6 = 0x00064000,
.EmcDllXformDqs7 = 0x00064000,
.EmcDllXformDqs8 = 0x00064000,
.EmcDllXformDqs9 = 0x00064000,
.EmcDllXformDqs10 = 0x00064000,
.EmcDllXformDqs11 = 0x00064000,
.EmcDllXformDqs12 = 0x00064000,
.EmcDllXformDqs13 = 0x00064000,
.EmcDllXformDqs14 = 0x00064000,
.EmcDllXformDqs15 = 0x00064000,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00000000,
.EmcDllXformAddr1 = 0x00000000,
.EmcDllXformAddr2 = 0x00004000,
.EmcDllXformAddr3 = 0x00000000,
.EmcDllXformAddr4 = 0x00000000,
.EmcDllXformAddr5 = 0x00004000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000000,
.EmcDliTrimTxDqs1 = 0x00000000,
.EmcDliTrimTxDqs2 = 0x00000000,
.EmcDliTrimTxDqs3 = 0x00000000,
.EmcDliTrimTxDqs4 = 0x00000000,
.EmcDliTrimTxDqs5 = 0x00000000,
.EmcDliTrimTxDqs6 = 0x00000000,
.EmcDliTrimTxDqs7 = 0x00000000,
.EmcDliTrimTxDqs8 = 0x00000000,
.EmcDliTrimTxDqs9 = 0x00000000,
.EmcDliTrimTxDqs10 = 0x00000000,
.EmcDliTrimTxDqs11 = 0x00000000,
.EmcDliTrimTxDqs12 = 0x00000000,
.EmcDliTrimTxDqs13 = 0x00000000,
.EmcDliTrimTxDqs14 = 0x00000000,
.EmcDliTrimTxDqs15 = 0x00000000,
.EmcDllXformDq0 = 0x00090000,
.EmcDllXformDq1 = 0x00090000,
.EmcDllXformDq2 = 0x00094000,
.EmcDllXformDq3 = 0x00094000,
.EmcDllXformDq4 = 0x00009400,
.EmcDllXformDq5 = 0x00009000,
.EmcDllXformDq6 = 0x00009000,
.EmcDllXformDq7 = 0x00009000,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x00000042,
.EmcZcalMrwCmd = 0x80000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x00000000,
.EmcZcalInitWait = 0x00000003,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000002,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x80001221,
.EmcWarmBootMrsExtra = 0x80100003,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fff2f97,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x10000280,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0130b118,
.EmcXm2DqsPadCtrl3 = 0x51451400,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x51451400,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc081,
.EmcXm2ClkPadCtrl2 = 0x00000303,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x0000003f,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0000003f,
.EmcTxdsrvttgen = 0x00000066,
.EmcBgbiasCtl0 = 0x00000008,
.McEmemAdrCfg = 0x00000000,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00000800,
.McEmemArbCfg = 0x01000003,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000001,
.McEmemArbTimingRp = 0x00000001,
.McEmemArbTimingRc = 0x00000005,
.McEmemArbTimingRas = 0x00000002,
.McEmemArbTimingFaw = 0x00000004,
.McEmemArbTimingRrd = 0x00000001,
.McEmemArbTimingRap2Pre = 0x00000002,
.McEmemArbTimingWap2Pre = 0x00000008,
.McEmemArbTimingR2R = 0x00000003,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000004,
.McEmemArbTimingW2R = 0x00000006,
.McEmemArbDaTurns = 0x06040203,
.McEmemArbDaCovers = 0x000a0405,
.McEmemArbMisc0 = 0x73840a06,
.McEmemArbMisc1 = 0x70000f03,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

311
src/mainboard/google/nyan_blaze/bct/sdram-hynix-2GB-792.inc Normal file
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{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x00000042,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000000,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000025,
.EmcRfc = 0x000000cc,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x0000001a,
.EmcRp = 0x00000009,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000008,
.EmcW2r = 0x0000000d,
.EmcR2p = 0x00000004,
.EmcW2p = 0x00000013,
.EmcRdRcd = 0x00000009,
.EmcWrRcd = 0x00000009,
.EmcRrd = 0x00000003,
.EmcRext = 0x00000002,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000006,
.EmcWdvMask = 0x00000006,
.EmcQUse = 0x0000000b,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000002,
.EmcEInputDuration = 0x0000000d,
.EmcPutermExtra = 0x00080000,
.EmcPutermWidth = 0x00000004,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000001,
.EmcQSafe = 0x00000014,
.EmcRdv = 0x00000018,
.EmcRdvMask = 0x0000001a,
.EmcQpop = 0x0000000f,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000004,
.EmcRefresh = 0x000017e2,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x000005f8,
.EmcPdEx2Wr = 0x00000003,
.EmcPdEx2Rd = 0x00000011,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x000000c6,
.EmcRw2Pden = 0x00000018,
.EmcTxsr = 0x000000d6,
.EmcTxsrDll = 0x00000200,
.EmcTcke = 0x00000005,
.EmcTckesr = 0x00000006,
.EmcTpd = 0x00000005,
.EmcTfaw = 0x0000001d,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x00000008,
.EmcTClkStop = 0x00000008,
.EmcTRefBw = 0x00001822,
.EmcFbioCfg5 = 0x104ab098,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x80000d71,
.EmcEmrs = 0x80100002,
.EmcEmrs2 = 0x80200018,
.EmcEmrs3 = 0x80300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x00f8000c,
.EmcMrsWaitCnt2 = 0x00f8000c,
.EmcCfg = 0x73300000,
.EmcCfg2 = 0x0000089d,
.EmcCfgPipe = 0x00004080,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80003012,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00700b1,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000002,
.EmcSelDpdCtrl = 0x00040000,
.EmcDllXformDqs0 = 0x00000008,
.EmcDllXformDqs1 = 0x00000008,
.EmcDllXformDqs2 = 0x00000008,
.EmcDllXformDqs3 = 0x00000008,
.EmcDllXformDqs4 = 0x00000008,
.EmcDllXformDqs5 = 0x00000008,
.EmcDllXformDqs6 = 0x00000008,
.EmcDllXformDqs7 = 0x00000008,
.EmcDllXformDqs8 = 0x00000008,
.EmcDllXformDqs9 = 0x00000008,
.EmcDllXformDqs10 = 0x00000008,
.EmcDllXformDqs11 = 0x00000008,
.EmcDllXformDqs12 = 0x00000008,
.EmcDllXformDqs13 = 0x00000008,
.EmcDllXformDqs14 = 0x00000008,
.EmcDllXformDqs15 = 0x00000008,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00034000,
.EmcDllXformAddr1 = 0x00034000,
.EmcDllXformAddr2 = 0x00000000,
.EmcDllXformAddr3 = 0x00034000,
.EmcDllXformAddr4 = 0x00034000,
.EmcDllXformAddr5 = 0x00000000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000008,
.EmcDliTrimTxDqs1 = 0x00000008,
.EmcDliTrimTxDqs2 = 0x00000005,
.EmcDliTrimTxDqs3 = 0x00000009,
.EmcDliTrimTxDqs4 = 0x00000009,
.EmcDliTrimTxDqs5 = 0x00000007,
.EmcDliTrimTxDqs6 = 0x00000009,
.EmcDliTrimTxDqs7 = 0x00000008,
.EmcDliTrimTxDqs8 = 0x00000008,
.EmcDliTrimTxDqs9 = 0x00000008,
.EmcDliTrimTxDqs10 = 0x00000005,
.EmcDliTrimTxDqs11 = 0x00000009,
.EmcDliTrimTxDqs12 = 0x00000009,
.EmcDliTrimTxDqs13 = 0x00000007,
.EmcDliTrimTxDqs14 = 0x00000009,
.EmcDliTrimTxDqs15 = 0x00000008,
.EmcDllXformDq0 = 0x0000000e,
.EmcDllXformDq1 = 0x0000000e,
.EmcDllXformDq2 = 0x0000000e,
.EmcDllXformDq3 = 0x0000000e,
.EmcDllXformDq4 = 0x0000000e,
.EmcDllXformDq5 = 0x0000000e,
.EmcDllXformDq6 = 0x0000000e,
.EmcDllXformDq7 = 0x0000000e,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x00000042,
.EmcZcalMrwCmd = 0x80000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x00000000,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x80000d71,
.EmcWarmBootMrsExtra = 0x80100002,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fff2f97,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x100002a0,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0120113d,
.EmcXm2DqsPadCtrl3 = 0x61861820,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x61861800,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc085,
.EmcXm2ClkPadCtrl2 = 0x00000101,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0606003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000000,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00000800,
.McEmemArbCfg = 0x0e00000b,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000004,
.McEmemArbTimingRp = 0x00000005,
.McEmemArbTimingRc = 0x00000013,
.McEmemArbTimingRas = 0x0000000c,
.McEmemArbTimingFaw = 0x0000000f,
.McEmemArbTimingRrd = 0x00000002,
.McEmemArbTimingRap2Pre = 0x00000003,
.McEmemArbTimingWap2Pre = 0x0000000c,
.McEmemArbTimingR2R = 0x00000002,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000006,
.McEmemArbTimingW2R = 0x00000008,
.McEmemArbDaTurns = 0x08060202,
.McEmemArbDaCovers = 0x00160d13,
.McEmemArbMisc0 = 0x734c2414,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

311
src/mainboard/google/nyan_blaze/bct/sdram-hynix-2GB-924.inc Normal file
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@ -0,0 +1,311 @@
{ /* generated from sdram-0001-924-2GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x0000004d,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430404,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000000,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x0000002b,
.EmcRfc = 0x000000ef,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x0000001e,
.EmcRp = 0x0000000b,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000008,
.EmcW2r = 0x0000000f,
.EmcR2p = 0x00000005,
.EmcW2p = 0x00000016,
.EmcRdRcd = 0x0000000b,
.EmcWrRcd = 0x0000000b,
.EmcRrd = 0x00000004,
.EmcRext = 0x00000002,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000006,
.EmcWdvMask = 0x00000006,
.EmcQUse = 0x0000000c,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000002,
.EmcEInputDuration = 0x0000000e,
.EmcPutermExtra = 0x000a0000,
.EmcPutermWidth = 0x00000004,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000001,
.EmcQSafe = 0x00000015,
.EmcRdv = 0x0000001b,
.EmcRdvMask = 0x0000001d,
.EmcQpop = 0x00000010,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000004,
.EmcRefresh = 0x00001be9,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x000006fa,
.EmcPdEx2Wr = 0x00000004,
.EmcPdEx2Rd = 0x00000015,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x000000e6,
.EmcRw2Pden = 0x0000001b,
.EmcTxsr = 0x000000fa,
.EmcTxsrDll = 0x00000200,
.EmcTcke = 0x00000006,
.EmcTckesr = 0x00000007,
.EmcTpd = 0x00000006,
.EmcTfaw = 0x00000022,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x0000000a,
.EmcTClkStop = 0x0000000a,
.EmcTRefBw = 0x00001c29,
.EmcFbioCfg5 = 0x104ab898,
.EmcFbioCfg6 = 0x00000002,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x80000f15,
.EmcEmrs = 0x80100002,
.EmcEmrs2 = 0x80200020,
.EmcEmrs3 = 0x80300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x00ce000e,
.EmcMrsWaitCnt2 = 0x00ce000e,
.EmcCfg = 0x73300000,
.EmcCfg2 = 0x000008a5,
.EmcCfgPipe = 0x00000000,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x800037ed,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00401b1,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000002,
.EmcSelDpdCtrl = 0x00040000,
.EmcDllXformDqs0 = 0x00000005,
.EmcDllXformDqs1 = 0x00000005,
.EmcDllXformDqs2 = 0x00000005,
.EmcDllXformDqs3 = 0x00000005,
.EmcDllXformDqs4 = 0x00000005,
.EmcDllXformDqs5 = 0x00000005,
.EmcDllXformDqs6 = 0x00000005,
.EmcDllXformDqs7 = 0x00000005,
.EmcDllXformDqs8 = 0x00000005,
.EmcDllXformDqs9 = 0x00000005,
.EmcDllXformDqs10 = 0x00000005,
.EmcDllXformDqs11 = 0x00000005,
.EmcDllXformDqs12 = 0x00000005,
.EmcDllXformDqs13 = 0x00000005,
.EmcDllXformDqs14 = 0x00000005,
.EmcDllXformDqs15 = 0x00000005,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x0000400e,
.EmcDllXformAddr1 = 0x0000400e,
.EmcDllXformAddr2 = 0x00000000,
.EmcDllXformAddr3 = 0x0000400e,
.EmcDllXformAddr4 = 0x0000400e,
.EmcDllXformAddr5 = 0x00000000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000000,
.EmcDliTrimTxDqs1 = 0x00000000,
.EmcDliTrimTxDqs2 = 0x00000000,
.EmcDliTrimTxDqs3 = 0x00000000,
.EmcDliTrimTxDqs4 = 0x00000000,
.EmcDliTrimTxDqs5 = 0x00000000,
.EmcDliTrimTxDqs6 = 0x00000000,
.EmcDliTrimTxDqs7 = 0x00000000,
.EmcDliTrimTxDqs8 = 0x00000000,
.EmcDliTrimTxDqs9 = 0x00000000,
.EmcDliTrimTxDqs10 = 0x00000000,
.EmcDliTrimTxDqs11 = 0x00000000,
.EmcDliTrimTxDqs12 = 0x00000000,
.EmcDliTrimTxDqs13 = 0x00000000,
.EmcDliTrimTxDqs14 = 0x00000000,
.EmcDliTrimTxDqs15 = 0x00000000,
.EmcDllXformDq0 = 0x00000006,
.EmcDllXformDq1 = 0x00000006,
.EmcDllXformDq2 = 0x00000006,
.EmcDllXformDq3 = 0x00000006,
.EmcDllXformDq4 = 0x00000006,
.EmcDllXformDq5 = 0x00000006,
.EmcDllXformDq6 = 0x00000006,
.EmcDllXformDq7 = 0x00000006,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x0000004c,
.EmcZcalMrwCmd = 0x80000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x00000000,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x80000f15,
.EmcWarmBootMrsExtra = 0x80100002,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fff2f97,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x100002a0,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0020013d,
.EmcXm2DqsPadCtrl3 = 0x55555520,
.EmcXm2DqsPadCtrl4 = 0x003cf3cf,
.EmcXm2DqsPadCtrl5 = 0x003cf3cf,
.EmcXm2DqsPadCtrl6 = 0x55555500,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc085,
.EmcXm2ClkPadCtrl2 = 0x00000303,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0606003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000000,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00000800,
.McEmemArbCfg = 0x0e00000d,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000005,
.McEmemArbTimingRp = 0x00000006,
.McEmemArbTimingRc = 0x00000016,
.McEmemArbTimingRas = 0x0000000e,
.McEmemArbTimingFaw = 0x00000011,
.McEmemArbTimingRrd = 0x00000002,
.McEmemArbTimingRap2Pre = 0x00000004,
.McEmemArbTimingWap2Pre = 0x0000000e,
.McEmemArbTimingR2R = 0x00000002,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000006,
.McEmemArbTimingW2R = 0x00000009,
.McEmemArbDaTurns = 0x09060202,
.McEmemArbDaCovers = 0x001a1016,
.McEmemArbMisc0 = 0x734e2a17,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

311
src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-204.inc Normal file
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{ /* generated from sdram-0100-204-4GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x00000022,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x40000002,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000001,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000009,
.EmcRfc = 0x00000047,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x00000007,
.EmcRp = 0x00000002,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000005,
.EmcW2r = 0x0000000a,
.EmcR2p = 0x00000003,
.EmcW2p = 0x0000000b,
.EmcRdRcd = 0x00000002,
.EmcWrRcd = 0x00000002,
.EmcRrd = 0x00000003,
.EmcRext = 0x00000003,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000005,
.EmcWdvMask = 0x00000005,
.EmcQUse = 0x00000006,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000004,
.EmcEInputDuration = 0x00000006,
.EmcPutermExtra = 0x00010000,
.EmcPutermWidth = 0x00000003,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000003,
.EmcQSafe = 0x0000000d,
.EmcRdv = 0x0000000f,
.EmcRdvMask = 0x00000011,
.EmcQpop = 0x0000000a,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000003,
.EmcRefresh = 0x00000607,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x00000181,
.EmcPdEx2Wr = 0x00000002,
.EmcPdEx2Rd = 0x00000002,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x00000044,
.EmcRw2Pden = 0x0000000f,
.EmcTxsr = 0x0000004a,
.EmcTxsrDll = 0x0000004a,
.EmcTcke = 0x00000004,
.EmcTckesr = 0x00000005,
.EmcTpd = 0x00000004,
.EmcTfaw = 0x00000007,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x00000005,
.EmcTClkStop = 0x00000005,
.EmcTRefBw = 0x00000638,
.EmcFbioCfg5 = 0x106aa298,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x00001221,
.EmcEmrs = 0x00100003,
.EmcEmrs2 = 0x00200008,
.EmcEmrs3 = 0x00300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x000c000c,
.EmcMrsWaitCnt2 = 0x000c000c,
.EmcCfg = 0x73240000,
.EmcCfg2 = 0x0000088d,
.EmcCfgPipe = 0x0000d2b3,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80000d22,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0x002c00a0,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000000,
.EmcSelDpdCtrl = 0x00040008,
.EmcDllXformDqs0 = 0x00064000,
.EmcDllXformDqs1 = 0x00064000,
.EmcDllXformDqs2 = 0x00064000,
.EmcDllXformDqs3 = 0x00064000,
.EmcDllXformDqs4 = 0x00064000,
.EmcDllXformDqs5 = 0x00064000,
.EmcDllXformDqs6 = 0x00064000,
.EmcDllXformDqs7 = 0x00064000,
.EmcDllXformDqs8 = 0x00064000,
.EmcDllXformDqs9 = 0x00064000,
.EmcDllXformDqs10 = 0x00064000,
.EmcDllXformDqs11 = 0x00064000,
.EmcDllXformDqs12 = 0x00064000,
.EmcDllXformDqs13 = 0x00064000,
.EmcDllXformDqs14 = 0x00064000,
.EmcDllXformDqs15 = 0x00064000,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00000000,
.EmcDllXformAddr1 = 0x00000000,
.EmcDllXformAddr2 = 0x00004000,
.EmcDllXformAddr3 = 0x00000000,
.EmcDllXformAddr4 = 0x00000000,
.EmcDllXformAddr5 = 0x00004000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000000,
.EmcDliTrimTxDqs1 = 0x00000000,
.EmcDliTrimTxDqs2 = 0x00000000,
.EmcDliTrimTxDqs3 = 0x00000000,
.EmcDliTrimTxDqs4 = 0x00000000,
.EmcDliTrimTxDqs5 = 0x00000000,
.EmcDliTrimTxDqs6 = 0x00000000,
.EmcDliTrimTxDqs7 = 0x00000000,
.EmcDliTrimTxDqs8 = 0x00000000,
.EmcDliTrimTxDqs9 = 0x00000000,
.EmcDliTrimTxDqs10 = 0x00000000,
.EmcDliTrimTxDqs11 = 0x00000000,
.EmcDliTrimTxDqs12 = 0x00000000,
.EmcDliTrimTxDqs13 = 0x00000000,
.EmcDliTrimTxDqs14 = 0x00000000,
.EmcDliTrimTxDqs15 = 0x00000000,
.EmcDllXformDq0 = 0x00090000,
.EmcDllXformDq1 = 0x00090000,
.EmcDllXformDq2 = 0x00094000,
.EmcDllXformDq3 = 0x00094000,
.EmcDllXformDq4 = 0x00009400,
.EmcDllXformDq5 = 0x00009000,
.EmcDllXformDq6 = 0x00009000,
.EmcDllXformDq7 = 0x00009000,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x00000042,
.EmcZcalMrwCmd = 0x00000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x40000011,
.EmcZcalInitWait = 0x00000003,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000002,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x00001221,
.EmcWarmBootMrsExtra = 0x00100003,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fffffff,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x10000280,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0130b118,
.EmcXm2DqsPadCtrl3 = 0x51451400,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x51451400,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc081,
.EmcXm2ClkPadCtrl2 = 0x00000303,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x0000003f,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0000003f,
.EmcTxdsrvttgen = 0x00000066,
.EmcBgbiasCtl0 = 0x00000008,
.McEmemAdrCfg = 0x00000001,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00001000,
.McEmemArbCfg = 0x01000003,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000001,
.McEmemArbTimingRp = 0x00000001,
.McEmemArbTimingRc = 0x00000005,
.McEmemArbTimingRas = 0x00000002,
.McEmemArbTimingFaw = 0x00000004,
.McEmemArbTimingRrd = 0x00000001,
.McEmemArbTimingRap2Pre = 0x00000002,
.McEmemArbTimingWap2Pre = 0x00000008,
.McEmemArbTimingR2R = 0x00000003,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000004,
.McEmemArbTimingW2R = 0x00000006,
.McEmemArbDaTurns = 0x06040203,
.McEmemArbDaCovers = 0x000a0405,
.McEmemArbMisc0 = 0x74a40a06,
.McEmemArbMisc1 = 0x70000f03,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

311
src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc Normal file
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{ /* generated from sdram-0100-792-4GB.cfg; do not edit. */
.MemoryType = NvBootMemoryType_Ddr3,
.PllMInputDivider = 0x00000001,
.PllMFeedbackDivider = 0x00000042,
.PllMStableTime = 0x0000012c,
.PllMSetupControl = 0x00000000,
.PllMSelectDiv2 = 0x00000000,
.PllMPDLshiftPh45 = 0x00000001,
.PllMPDLshiftPh90 = 0x00000001,
.PllMPDLshiftPh135 = 0x00000001,
.PllMKCP = 0x00000000,
.PllMKVCO = 0x00000000,
.EmcBctSpare0 = 0x00000000,
.EmcBctSpare1 = 0x00000000,
.EmcBctSpare2 = 0x00000000,
.EmcBctSpare3 = 0x00000000,
.EmcBctSpare4 = 0x00000000,
.EmcBctSpare5 = 0x00000000,
.EmcBctSpare6 = 0x00000000,
.EmcBctSpare7 = 0x00000000,
.EmcBctSpare8 = 0x00000000,
.EmcBctSpare9 = 0x00000000,
.EmcBctSpare10 = 0x00000000,
.EmcBctSpare11 = 0x00000000,
.EmcClockSource = 0x80000000,
.EmcAutoCalInterval = 0x001fffff,
.EmcAutoCalConfig = 0xa1430000,
.EmcAutoCalConfig2 = 0x00000000,
.EmcAutoCalConfig3 = 0x00000000,
.EmcAutoCalWait = 0x00000190,
.EmcAdrCfg = 0x00000001,
.EmcPinProgramWait = 0x00000001,
.EmcPinExtraWait = 0x00000000,
.EmcTimingControlWait = 0x00000000,
.EmcRc = 0x00000025,
.EmcRfc = 0x00000114,
.EmcRfcSlr = 0x00000000,
.EmcRas = 0x0000001a,
.EmcRp = 0x00000007,
.EmcR2r = 0x00000000,
.EmcW2w = 0x00000000,
.EmcR2w = 0x00000008,
.EmcW2r = 0x0000000d,
.EmcR2p = 0x00000004,
.EmcW2p = 0x00000013,
.EmcRdRcd = 0x00000009,
.EmcWrRcd = 0x00000009,
.EmcRrd = 0x00000003,
.EmcRext = 0x00000002,
.EmcWext = 0x00000000,
.EmcWdv = 0x00000006,
.EmcWdvMask = 0x00000006,
.EmcQUse = 0x0000000b,
.EmcQuseWidth = 0x00000002,
.EmcIbdly = 0x00000000,
.EmcEInput = 0x00000002,
.EmcEInputDuration = 0x0000000d,
.EmcPutermExtra = 0x00080000,
.EmcPutermWidth = 0x00000004,
.EmcPutermAdj = 0x00000000,
.EmcCdbCntl1 = 0x00000000,
.EmcCdbCntl2 = 0x00000000,
.EmcCdbCntl3 = 0x00000000,
.EmcQRst = 0x00000001,
.EmcQSafe = 0x00000014,
.EmcRdv = 0x00000018,
.EmcRdvMask = 0x0000001a,
.EmcQpop = 0x0000000f,
.EmcCtt = 0x00000000,
.EmcCttDuration = 0x00000004,
.EmcRefresh = 0x000017e2,
.EmcBurstRefreshNum = 0x00000000,
.EmcPreRefreshReqCnt = 0x000005f8,
.EmcPdEx2Wr = 0x00000003,
.EmcPdEx2Rd = 0x00000011,
.EmcPChg2Pden = 0x00000001,
.EmcAct2Pden = 0x00000000,
.EmcAr2Pden = 0x0000010d,
.EmcRw2Pden = 0x00000018,
.EmcTxsr = 0x0000011e,
.EmcTxsrDll = 0x00000200,
.EmcTcke = 0x00000005,
.EmcTckesr = 0x00000006,
.EmcTpd = 0x00000005,
.EmcTfaw = 0x0000001d,
.EmcTrpab = 0x00000000,
.EmcTClkStable = 0x00000008,
.EmcTClkStop = 0x00000008,
.EmcTRefBw = 0x00001822,
.EmcFbioCfg5 = 0x104ab098,
.EmcFbioCfg6 = 0x00000000,
.EmcFbioSpare = 0x00000000,
.EmcCfgRsv = 0xff00ff00,
.EmcMrs = 0x00000d71,
.EmcEmrs = 0x00100002,
.EmcEmrs2 = 0x00200018,
.EmcEmrs3 = 0x00300000,
.EmcMrw1 = 0x00000000,
.EmcMrw2 = 0x00000000,
.EmcMrw3 = 0x00000000,
.EmcMrw4 = 0x00000000,
.EmcMrwExtra = 0x00000000,
.EmcWarmBootMrwExtra = 0x00000000,
.EmcWarmBootExtraModeRegWriteEnable = 0x00000000,
.EmcExtraModeRegWriteEnable = 0x00000000,
.EmcMrwResetCommand = 0x00000000,
.EmcMrwResetNInitWait = 0x00000000,
.EmcMrsWaitCnt = 0x006f000c,
.EmcMrsWaitCnt2 = 0x006f000c,
.EmcCfg = 0x73300000,
.EmcCfg2 = 0x0000089d,
.EmcCfgPipe = 0x00004080,
.EmcDbg = 0x01000c00,
.EmcCmdQ = 0x10004408,
.EmcMc2EmcQ = 0x06000404,
.EmcDynSelfRefControl = 0x80003012,
.AhbArbitrationXbarCtrlMemInitDone = 0x00000001,
.EmcCfgDigDll = 0xe00700b1,
.EmcCfgDigDllPeriod = 0x00008000,
.EmcDevSelect = 0x00000000,
.EmcSelDpdCtrl = 0x00040000,
.EmcDllXformDqs0 = 0x00000008,
.EmcDllXformDqs1 = 0x00000008,
.EmcDllXformDqs2 = 0x00000008,
.EmcDllXformDqs3 = 0x00000008,
.EmcDllXformDqs4 = 0x00000008,
.EmcDllXformDqs5 = 0x00000008,
.EmcDllXformDqs6 = 0x00000008,
.EmcDllXformDqs7 = 0x00000008,
.EmcDllXformDqs8 = 0x00000008,
.EmcDllXformDqs9 = 0x00000008,
.EmcDllXformDqs10 = 0x00000008,
.EmcDllXformDqs11 = 0x00000008,
.EmcDllXformDqs12 = 0x00000008,
.EmcDllXformDqs13 = 0x00000008,
.EmcDllXformDqs14 = 0x00000008,
.EmcDllXformDqs15 = 0x00000008,
.EmcDllXformQUse0 = 0x00000000,
.EmcDllXformQUse1 = 0x00000000,
.EmcDllXformQUse2 = 0x00000000,
.EmcDllXformQUse3 = 0x00000000,
.EmcDllXformQUse4 = 0x00000000,
.EmcDllXformQUse5 = 0x00000000,
.EmcDllXformQUse6 = 0x00000000,
.EmcDllXformQUse7 = 0x00000000,
.EmcDllXformAddr0 = 0x00034000,
.EmcDllXformAddr1 = 0x00034000,
.EmcDllXformAddr2 = 0x00000000,
.EmcDllXformAddr3 = 0x00034000,
.EmcDllXformAddr4 = 0x00034000,
.EmcDllXformAddr5 = 0x00000000,
.EmcDllXformQUse8 = 0x00000000,
.EmcDllXformQUse9 = 0x00000000,
.EmcDllXformQUse10 = 0x00000000,
.EmcDllXformQUse11 = 0x00000000,
.EmcDllXformQUse12 = 0x00000000,
.EmcDllXformQUse13 = 0x00000000,
.EmcDllXformQUse14 = 0x00000000,
.EmcDllXformQUse15 = 0x00000000,
.EmcDliTrimTxDqs0 = 0x00000008,
.EmcDliTrimTxDqs1 = 0x00000008,
.EmcDliTrimTxDqs2 = 0x00000005,
.EmcDliTrimTxDqs3 = 0x00000009,
.EmcDliTrimTxDqs4 = 0x00000009,
.EmcDliTrimTxDqs5 = 0x00000007,
.EmcDliTrimTxDqs6 = 0x00000009,
.EmcDliTrimTxDqs7 = 0x00000008,
.EmcDliTrimTxDqs8 = 0x00000008,
.EmcDliTrimTxDqs9 = 0x00000008,
.EmcDliTrimTxDqs10 = 0x00000005,
.EmcDliTrimTxDqs11 = 0x00000009,
.EmcDliTrimTxDqs12 = 0x00000009,
.EmcDliTrimTxDqs13 = 0x00000007,
.EmcDliTrimTxDqs14 = 0x00000009,
.EmcDliTrimTxDqs15 = 0x00000008,
.EmcDllXformDq0 = 0x0000000e,
.EmcDllXformDq1 = 0x0000000e,
.EmcDllXformDq2 = 0x0000000e,
.EmcDllXformDq3 = 0x0000000e,
.EmcDllXformDq4 = 0x0000000e,
.EmcDllXformDq5 = 0x0000000e,
.EmcDllXformDq6 = 0x0000000e,
.EmcDllXformDq7 = 0x0000000e,
.WarmBootWait = 0x00000002,
.EmcCttTermCtrl = 0x00000802,
.EmcOdtWrite = 0x00000000,
.EmcOdtRead = 0x00000000,
.EmcZcalInterval = 0x00020000,
.EmcZcalWaitCnt = 0x00000042,
.EmcZcalMrwCmd = 0x00000000,
.EmcMrsResetDll = 0x00000000,
.EmcZcalInitDev0 = 0x80000011,
.EmcZcalInitDev1 = 0x40000011,
.EmcZcalInitWait = 0x00000001,
.EmcZcalWarmColdBootEnables = 0x00000003,
.EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab,
.EmcZqCalDdr3WarmBoot = 0x00000000,
.EmcZcalWarmBootWait = 0x00000001,
.EmcMrsWarmBootEnable = 0x00000001,
.EmcMrsResetDllWait = 0x00000000,
.EmcMrsExtra = 0x00000d71,
.EmcWarmBootMrsExtra = 0x00100002,
.EmcEmrsDdr2DllEnable = 0x00000000,
.EmcMrsDdr2DllReset = 0x00000000,
.EmcEmrsDdr2OcdCalib = 0x00000000,
.EmcDdr2Wait = 0x00000000,
.EmcClkenOverride = 0x00000000,
.McDisExtraSnapLevels = 0x00000000,
.EmcExtraRefreshNum = 0x00000002,
.EmcClkenOverrideAllWarmBoot = 0x00000000,
.McClkenOverrideAllWarmBoot = 0x00000000,
.EmcCfgDigDllPeriodWarmBoot = 0x00000003,
.PmcVddpSel = 0x00000002,
.PmcVddpSelWait = 0x00000002,
.PmcDdrPwr = 0x00000003,
.PmcDdrCfg = 0x00002002,
.PmcIoDpd3Req = 0x4fffffff,
.PmcIoDpd3ReqWait = 0x00000000,
.PmcRegShort = 0x00000000,
.PmcNoIoPower = 0x00000000,
.PmcPorDpdCtrlWait = 0x00000000,
.EmcXm2CmdPadCtrl = 0x100002a0,
.EmcXm2CmdPadCtrl2 = 0x770c0000,
.EmcXm2CmdPadCtrl3 = 0x050c0000,
.EmcXm2CmdPadCtrl4 = 0x00000000,
.EmcXm2CmdPadCtrl5 = 0x00111111,
.EmcXm2DqsPadCtrl = 0x770c1414,
.EmcXm2DqsPadCtrl2 = 0x0120113d,
.EmcXm2DqsPadCtrl3 = 0x61861820,
.EmcXm2DqsPadCtrl4 = 0x00514514,
.EmcXm2DqsPadCtrl5 = 0x00514514,
.EmcXm2DqsPadCtrl6 = 0x61861800,
.EmcXm2DqPadCtrl = 0x770c2990,
.EmcXm2DqPadCtrl2 = 0x00000000,
.EmcXm2DqPadCtrl3 = 0x00000000,
.EmcXm2ClkPadCtrl = 0x77ffc085,
.EmcXm2ClkPadCtrl2 = 0x00000101,
.EmcXm2CompPadCtrl = 0x81f1f108,
.EmcXm2VttGenPadCtrl = 0x07070004,
.EmcXm2VttGenPadCtrl2 = 0x00000000,
.EmcXm2VttGenPadCtrl3 = 0x016eeeee,
.EmcAcpdControl = 0x00000000,
.EmcSwizzleRank0ByteCfg = 0x00003120,
.EmcSwizzleRank0Byte0 = 0x25143067,
.EmcSwizzleRank0Byte1 = 0x45367102,
.EmcSwizzleRank0Byte2 = 0x47106253,
.EmcSwizzleRank0Byte3 = 0x04362175,
.EmcSwizzleRank1ByteCfg = 0x00003120,
.EmcSwizzleRank1Byte0 = 0x71546032,
.EmcSwizzleRank1Byte1 = 0x35104276,
.EmcSwizzleRank1Byte2 = 0x27043615,
.EmcSwizzleRank1Byte3 = 0x72306145,
.EmcDsrVttgenDrv = 0x0606003f,
.EmcTxdsrvttgen = 0x00000000,
.EmcBgbiasCtl0 = 0x00000000,
.McEmemAdrCfg = 0x00000001,
.McEmemAdrCfgDev0 = 0x00080303,
.McEmemAdrCfgDev1 = 0x00080303,
.McEmemAdrCfgBankMask0 = 0x00001248,
.McEmemAdrCfgBankMask1 = 0x00002490,
.McEmemAdrCfgBankMask2 = 0x00000920,
.McEmemAdrCfgBankSwizzle3 = 0x00000001,
.McEmemCfg = 0x00001000,
.McEmemArbCfg = 0x0e00000b,
.McEmemArbOutstandingReq = 0x80000040,
.McEmemArbTimingRcd = 0x00000004,
.McEmemArbTimingRp = 0x00000004,
.McEmemArbTimingRc = 0x00000013,
.McEmemArbTimingRas = 0x0000000c,
.McEmemArbTimingFaw = 0x0000000f,
.McEmemArbTimingRrd = 0x00000002,
.McEmemArbTimingRap2Pre = 0x00000003,
.McEmemArbTimingWap2Pre = 0x0000000c,
.McEmemArbTimingR2R = 0x00000002,
.McEmemArbTimingW2W = 0x00000002,
.McEmemArbTimingR2W = 0x00000006,
.McEmemArbTimingW2R = 0x00000008,
.McEmemArbDaTurns = 0x08060202,
.McEmemArbDaCovers = 0x00150c13,
.McEmemArbMisc0 = 0x746c2414,
.McEmemArbMisc1 = 0x70000f02,
.McEmemArbRing1Throttle = 0x001f0000,
.McEmemArbOverride = 0x10000000,
.McEmemArbOverride1 = 0x00000000,
.McEmemArbRsv = 0xff00ff00,
.McClkenOverride = 0x00000000,
.McStatControl = 0x00000000,
.McDisplaySnapRing = 0x00000003,
.McVideoProtectBom = 0xfff00000,
.McVideoProtectBomAdrHi = 0x00000000,
.McVideoProtectSizeMb = 0x00000000,
.McVideoProtectVprOverride = 0xe4bac743,
.McVideoProtectVprOverride1 = 0x00000013,
.McVideoProtectGpuOverride0 = 0x00000000,
.McVideoProtectGpuOverride1 = 0x00000000,
.McSecCarveoutBom = 0xfff00000,
.McSecCarveoutAdrHi = 0x00000000,
.McSecCarveoutSizeMb = 0x00000000,
.McVideoProtectWriteAccess = 0x00000000,
.McSecCarveoutProtectWriteAccess = 0x00000000,
.EmcCaTrainingEnable = 0x00000000,
.EmcCaTrainingTimingCntl1 = 0x1f7df7df,
.EmcCaTrainingTimingCntl2 = 0x0000001f,
.SwizzleRankByteEncode = 0x0000006f,
.BootRomPatchControl = 0x00000000,
.BootRomPatchData = 0x00000000,
.McMtsCarveoutBom = 0xfff00000,
.McMtsCarveoutAdrHi = 0x00000000,
.McMtsCarveoutSizeMb = 0x00000000,
.McMtsCarveoutRegCtrl = 0x00000000,
},

4
src/mainboard/google/nyan_blaze/bct/sdram-unused.inc Normal file
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{ /* dummy. */
.MemoryType = NvBootMemoryType_Unused,
0,
},

34
src/mainboard/google/nyan_blaze/bct/spi.cfg Normal file
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# Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
# Distributed under the terms of the GNU General Public License v2
Version = 0x00350001;
BlockSize = 32768;
PageSize = 2048;
PartitionSize = 4194304;
Bctcopy = 1;
DevType[0] = NvBootDevType_Spi;
DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[0].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0;
DevType[1] = NvBootDevType_Spi;
DeviceParam[1].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[1].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[1].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[1].SpiFlashParams.PageSize2kor16k = 0;
DevType[2] = NvBootDevType_Spi;
DeviceParam[2].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[2].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[2].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[2].SpiFlashParams.PageSize2kor16k = 0;
DevType[3] = NvBootDevType_Spi;
DeviceParam[3].SpiFlashParams.ReadCommandTypeFast = NV_FALSE;
DeviceParam[3].SpiFlashParams.ClockDivider = 0x16;
DeviceParam[3].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0;
DeviceParam[3].SpiFlashParams.PageSize2kor16k = 0;

45
src/mainboard/google/nyan_blaze/boardid.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <stdlib.h>
#include "boardid.h"
uint8_t board_id(void)
{
static int id = -1;
if (id < 0) {
gpio_t gpio[] = {GPIO(Q3), GPIO(T1), GPIO(X1), GPIO(X4)};
int value[ARRAY_SIZE(gpio)];
gpio_get_in_tristate_values(gpio, ARRAY_SIZE(gpio), value);
/* A gpio state is encoded in every two-bit */
id = value[0] << 0 |
value[1] << 2 |
value[2] << 4 |
value[3] << 6;
printk(BIOS_SPEW, "Board TRISTATE ID: %#x.\n", id);
}
return id;
}

27
src/mainboard/google/nyan_blaze/boardid.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BLAZE_BOARDID_H__
#define __MAINBOARD_GOOGLE_NYAN_BLAZE_BOARDID_H__
#include <stdint.h>
uint8_t board_id(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_BLAZE_BOARDID_H__ */

90
src/mainboard/google/nyan_blaze/bootblock.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <device/i2c.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/clk_rst.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <soc/nvidia/tegra124/pinmux.h>
#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */
#include "pmic.h"
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void set_clock_sources(void)
{
/* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */
writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta);
clock_configure_source(mselect, PLLP, 102000);
/* The PMIC is on I2C5 and can run at 400 KHz. */
clock_configure_i2c_scl_freq(i2c5, PLLP, 400);
/* TODO: We should be able to set this to 50MHz, but that did not seem
* reliable. */
clock_configure_source(sbc4, PLLP, 33333);
}
void bootblock_mainboard_init(void)
{
set_clock_sources();
clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR,
CLK_H_I2C5 | CLK_H_APBDMA,
0, CLK_V_MSELECT, 0, 0);
// Board ID GPIOs, bits 0-3.
gpio_input(GPIO(Q3));
gpio_input(GPIO(T1));
gpio_input(GPIO(X1));
gpio_input(GPIO(X4));
// I2C5 (PMU) clock.
pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX,
PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
// I2C5 (PMU) data.
pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX,
PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE);
i2c_init(4);
pmic_init(4);
/* SPI4 data out (MOSI) */
pinmux_set_config(PINMUX_GPIO_PG6_INDEX,
PINMUX_GPIO_PG6_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 data in (MISO) */
pinmux_set_config(PINMUX_GPIO_PG7_INDEX,
PINMUX_GPIO_PG7_FUNC_SPI4 | PINMUX_INPUT_ENABLE |
PINMUX_PULL_UP);
/* SPI4 clock */
pinmux_set_config(PINMUX_GPIO_PG5_INDEX,
PINMUX_GPIO_PG5_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
/* SPI4 chip select 0 */
pinmux_set_config(PINMUX_GPIO_PI3_INDEX,
PINMUX_GPIO_PI3_FUNC_SPI4 | PINMUX_INPUT_ENABLE);
tegra_spi_init(4);
}

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src/mainboard/google/nyan_blaze/chromeos.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <boot/coreboot_tables.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include <ec/google/chromeec/ec_commands.h>
#include <string.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <soc/nvidia/tegra124/gpio.h>
//enum {
// ACTIVE_LOW = 0,
// ACTIVE_HIGH = 1
//};
void fill_lb_gpios(struct lb_gpios *gpios)
{
int count = 0;
/* Write Protect: active low */
gpios->gpios[count].port = GPIO_R1_INDEX;
gpios->gpios[count].polarity = ACTIVE_LOW;
gpios->gpios[count].value = gpio_get_in_value(GPIO(R1));
strncpy((char *)gpios->gpios[count].name, "write protect",
GPIO_MAX_NAME_LENGTH);
count++;
/* Recovery: active high */
gpios->gpios[count].port = -1;
gpios->gpios[count].polarity = ACTIVE_HIGH;
gpios->gpios[count].value = get_recovery_mode_switch();
strncpy((char *)gpios->gpios[count].name, "recovery",
GPIO_MAX_NAME_LENGTH);
count++;
/* Lid: active high */
gpios->gpios[count].port = GPIO_R4_INDEX;
gpios->gpios[count].polarity = ACTIVE_HIGH;
gpios->gpios[count].value = gpio_get_in_value(GPIO(R4));
strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH);
count++;
/* Power: active low */
gpios->gpios[count].port = GPIO_Q0_INDEX;
gpios->gpios[count].polarity = ACTIVE_LOW;
gpios->gpios[count].value = gpio_get_in_value(GPIO(Q0));
strncpy((char *)gpios->gpios[count].name, "power",
GPIO_MAX_NAME_LENGTH);
count++;
/* Developer: virtual GPIO active high */
gpios->gpios[count].port = -1;
gpios->gpios[count].polarity = ACTIVE_HIGH;
gpios->gpios[count].value = get_developer_mode_switch();
strncpy((char *)gpios->gpios[count].name, "developer",
GPIO_MAX_NAME_LENGTH);
count++;
gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio));
gpios->count = count;
printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size);
}
int get_developer_mode_switch(void)
{
return 0;
}
int get_recovery_mode_switch(void)
{
uint32_t ec_events;
/* The GPIO is active low. */
if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO
return 1;
ec_events = google_chromeec_get_events_b();
return !!(ec_events &
EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
}
int get_write_protect_state(void)
{
return !gpio_get_in_value(GPIO(R1));
}

80
src/mainboard/google/nyan_blaze/devicetree.cb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright 2014 Google Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
chip soc/nvidia/tegra124
device cpu_cluster 0 on end
# N.B. We ae not using the device tree in an effective way.
# We need to change this in future such that the on-soc
# devices are 'chips', which will allow us to go at them
# in parallel. This is even easier on the ARM SOCs since there
# are no single-access resources such as the infamous
# cf8/cfc registers found on PCs.
register "display_controller" = "TEGRA_ARM_DISPLAYA"
register "xres" = "1366"
register "yres" = "768"
# this setting is what nvidia does; it makes no sense
# and does not agree with hardware. Why'd they do it?
register "framebuffer_bits_per_pixel" = "18"
register "cache_policy" = "DCACHE_WRITETHROUGH"
# With some help from the mainbaord designer
register "backlight_en_gpio" = "GPIO(H2)"
register "lvds_shutdown_gpio" = "0"
register "backlight_vdd_gpio" = "GPIO(P2)"
register "panel_vdd_gpio" = "0"
register "pwm" = "1"
# taken from u-boot; these look wrong however.
register "vdd_delay" = "400"
register "vdd_data_delay" = "4"
register "data_backlight_delay" = "203"
register "backlight_pwm_delay" = "17"
register "pwm_backlight_en_delay" = "15"
# How to compute these: xrandr --verbose will give you this:
#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
# 2560 2608 2640 2720 hborder 0
# 1700 1703 1713 1749 vborder 0
#Then you can compute your values:
#H front porch = 2608 - 2560 = 48
#H sync = 2640 - 2608 = 32
#H back porch = 2720 - 2640 = 80
#V front porch = 1703 - 1700 = 3
#V sync = 1713 - 1703 = 10
#V back porch = 1749 - 1713 = 36
#href_to_sync and vref_to_sync are from the vendor
#this is just an example for a Pixel panel; other panels differ.
# Here is a peppy panel:
# 1366x768 (0x45) 76.4MHz -HSync -VSync *current +preferred
# h: width 1366 start 1502 end 1532 total 1592
# v: height 768 start 776 end 788 total 800
# These numbers were provided by Nvidia.
register "href_to_sync" = "1"
register "hfront_porch" = "44"
register "hsync_width" = "46"
register "hback_porch" = "44"
register "vref_to_sync" = "1"
register "vfront_porch" = "6"
register "vsync_width" = "8"
register "vback_porch" = "6"
# we *know* the pixel clock for this system.
register "pixel_clock" = "71"
end

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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <device/device.h>
#include <boot/coreboot_tables.h>
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/nvidia/tegra/i2c.h>
#include <soc/nvidia/tegra124/clk_rst.h>
#include <soc/nvidia/tegra124/gpio.h>
#include <soc/nvidia/tegra124/mc.h>
#include <soc/nvidia/tegra124/pmc.h>
#include <soc/nvidia/tegra124/spi.h>
#include <soc/nvidia/tegra124/usb.h>
static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
static void set_clock_sources(void)
{
/*
* The max98090 codec and the temperature sensor are on I2C1. These
* can both run at 400 KHz, but the kernel sets the bus to 100 KHz.
*/
clock_configure_i2c_scl_freq(i2c1, PLLP, 100);
/*
* The TPM is on I2C3 and can theoretically run at 400 KHz but doesn't
* seem to work above around 40 KHz. It's set to run at 100 KHz in the
* kernel.
*/
clock_configure_i2c_scl_freq(i2c3, PLLP, 40);
clock_configure_source(sbc1, PLLP, 5000);
/*
* MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's
* maximum speed (48MHz) so we can change SDCLK by second stage divisor
* in payloads, without touching base clock.
*/
clock_configure_source(sdmmc3, PLLP, 48000);
clock_configure_source(sdmmc4, PLLP, 48000);
/* External peripheral 1: audio codec (max98090) using 12MHz CLK1.
* Note the source id of CLK_M for EXTPERIPH1 is 3. */
clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3);
/*
* I2S1 can use either PLLP or PLLA. Using PLLP is sufficient now since
* we only need 4.8MHz. Note the source id of PLLP for I2S is 4.
*/
clock_configure_irregular_source(i2s1, PLLP, 4800, 4);
/* Note source id of PLLP for HOST1x is 4. */
clock_configure_irregular_source(host1x, PLLP, 408000, 4);
/* Use PLLD_OUT0 as clock source for disp1 */
clrsetbits_le32(&clk_rst->clk_src_disp1,
CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
}
static void setup_pinmux(void)
{
// Write protect.
gpio_input_pullup(GPIO(R1));
// Recovery mode.
gpio_input_pullup(GPIO(Q7));
// Lid switch.
gpio_input_pullup(GPIO(R4));
// Power switch.
gpio_input_pullup(GPIO(Q0));
// Developer mode.
gpio_input_pullup(GPIO(Q6));
// EC in RW.
gpio_input_pullup(GPIO(U4));
// SOC and TPM reset GPIO, active low.
gpio_output(GPIO(I5), 1);
// SPI1 MOSI
pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 MISO
pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 SCLK
pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// SPI1 CS0
pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 |
PINMUX_PULL_NONE |
PINMUX_INPUT_ENABLE);
// switch unused pin to GPIO
gpio_set_mode(GPIO(X3), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X4), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X5), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X6), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(X7), GPIO_MODE_GPIO);
gpio_set_mode(GPIO(W3), GPIO_MODE_GPIO);
// I2C1 clock.
pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX,
PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
// I2C1 data.
pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX,
PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
// I2C2 clock.
pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
// I2C2 data.
pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE);
// I2C3 (cam) clock.
pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX,
PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// I2C3 (cam) data.
pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX,
PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE);
// I2C4 (DDC) clock.
pinmux_set_config(PINMUX_DDC_SCL_INDEX,
PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
// I2C4 (DDC) data.
pinmux_set_config(PINMUX_DDC_SDA_INDEX,
PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
// TODO(hungte) Revice pinmux setup, make nice little SoC functions for
// every single logical thing instead of dumping a wall of code below.
uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE,
pin_up3 = (PINMUX_PULL_UP | PINMUX_INPUT_ENABLE |
PINMUX_TRISTATE),
pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE,
pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE;
// MMC3
pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX,
PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none);
pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX,
PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up);
pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX,
PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up);
pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX,
PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up);
pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX,
PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up);
pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX,
PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up);
pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX,
PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up3);
pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX,
PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down);
// MMC3 Card Detect pin.
gpio_input_pullup(GPIO(V2));
// Enable MMC power.
gpio_output(GPIO(R0), 1);
// MMC4
pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX,
PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none);
pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX,
PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up);
pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX,
PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up);
pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX,
PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up);
pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX,
PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up);
pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX,
PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up);
pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX,
PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up);
pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX,
PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up);
pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX,
PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up);
pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX,
PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up);
/* We pull the USB VBUS signals up but keep them as inputs since the
* voltage source likes to drive them low on overcurrent conditions */
gpio_input_pullup(GPIO(N4)); /* USB VBUS EN0 */
gpio_input_pullup(GPIO(N5)); /* USB VBUS EN1 */
/* Clock output 1 (for external peripheral) */
pinmux_set_config(PINMUX_DAP_MCLK1_INDEX,
PINMUX_DAP_MCLK1_FUNC_EXTPERIPH1 | PINMUX_PULL_NONE);
/* I2S1 */
pinmux_set_config(PINMUX_DAP2_DIN_INDEX,
PINMUX_DAP2_DIN_FUNC_I2S1 | PINMUX_TRISTATE |
PINMUX_INPUT_ENABLE);
pinmux_set_config(PINMUX_DAP2_DOUT_INDEX,
PINMUX_DAP2_DOUT_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
pinmux_set_config(PINMUX_DAP2_FS_INDEX,
PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
pinmux_set_config(PINMUX_DAP2_SCLK_INDEX,
PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
/* PWM1 */
pinmux_set_config(PINMUX_GPIO_PH1_INDEX,
PINMUX_GPIO_PH1_FUNC_PWM1 | PINMUX_PULL_NONE);
}
static void setup_kernel_info(void)
{
// Setup required information for Linux kernel.
// pmc.odmdata: [18:19]: console type, [15:17]: UART id.
// TODO(hungte) This should be done by filling BCT values, or derived
// from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
// value defined in BCT.
struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
writel(0x80080000, &pmc->odmdata);
// Not strictly info, but kernel graphics driver needs this region locked down
struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
writel(0, &mc->video_protect_bom);
writel(0, &mc->video_protect_size_mb);
writel(1, &mc->video_protect_reg_ctrl);
}
static void setup_ec_spi(void)
{
struct tegra_spi_channel *spi;
spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
/* Set frame header for use by CrOS EC */
spi->frame_header = 0xec;
spi->rx_frame_header_enable = 1;
}
static void mainboard_init(device_t dev)
{
set_clock_sources();
clock_external_output(1); /* For external MAX98090 audio codec. */
/*
* Confirmed by NVIDIA hardware team, we need to take ALL audio devices
* conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
* of reset and clock-enabled, otherwise reading AHUB devices (In our
* case, I2S/APBIF/AUDIO<XBAR>) will hang.
*/
clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
CLK_L_HOST1X | CLK_L_PWM,
CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 |
CLK_H_PMC | CLK_H_MEM | CLK_H_USB3,
CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3,
CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
CLK_X_AFC5);
usb_setup_utmip1();
/* USB2 is the camera, we don't need it in firmware */
usb_setup_utmip3();
setup_pinmux();
i2c_init(0);
i2c_init(1);
i2c_init(2);
i2c_init(3);
setup_kernel_info();
clock_init_arm_generic_timer();
setup_ec_spi();
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
}
struct chip_operations mainboard_ops = {
.name = "nyan_blaze",
.enable_dev = mainboard_enable,
};
void lb_board(struct lb_header *header)
{
struct lb_range *dma;
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = CONFIG_DRAM_DMA_START;
dma->range_size = CONFIG_DRAM_DMA_SIZE;
}

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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
* Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <delay.h>
#include <device/i2c.h>
#include <stdint.h>
#include <stdlib.h>
#include "boardid.h"
#include "pmic.h"
enum {
AS3722_I2C_ADDR = 0x40
};
struct as3722_init_reg {
u8 reg;
u8 val;
u8 delay;
};
static struct as3722_init_reg init_list[] = {
{AS3722_SDO0, 0x3C, 1},
{AS3722_SDO1, 0x32, 0},
{AS3722_LDO3, 0x59, 0},
{AS3722_SDO2, 0x3C, 0},
{AS3722_SDO3, 0x00, 0},
{AS3722_SDO4, 0x00, 0},
{AS3722_SDO5, 0x50, 0},
{AS3722_SDO6, 0x28, 1},
{AS3722_LDO0, 0x8A, 0},
{AS3722_LDO1, 0x00, 0},
{AS3722_LDO2, 0x10, 0},
{AS3722_LDO4, 0x00, 0},
{AS3722_LDO5, 0x00, 0},
{AS3722_LDO6, 0x3F, 0},
{AS3722_LDO7, 0x00, 0},
{AS3722_LDO9, 0x00, 0},
{AS3722_LDO10, 0x00, 0},
{AS3722_LDO11, 0x00, 1},
};
static void pmic_write_reg(unsigned bus, uint8_t reg, uint8_t val, int do_delay)
{
i2c_write(bus, AS3722_I2C_ADDR, reg, 1, &val, 1);
if (do_delay)
udelay(500);
}
static void pmic_slam_defaults(unsigned bus)
{
int i;
for (i = 0; i < ARRAY_SIZE(init_list); i++) {
struct as3722_init_reg *reg = &init_list[i];
pmic_write_reg(bus, reg->reg, reg->val, reg->delay);
}
}
void pmic_init(unsigned bus)
{
/*
* Don't need to set up VDD_CORE - already done - by OTP
* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled.
* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled.
*/
/* Restore PMIC POR defaults, in case kernel changed 'em */
pmic_slam_defaults(bus);
/* First set VDD_CPU to 1.2V, then enable the VDD_CPU regulator. */
pmic_write_reg(bus, 0x00, 0x50, 1);
/* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */
pmic_write_reg(bus, 0x06, 0x28, 1);
/*
* First set +1.2V_GEN_AVDD to 1.2V, then enable the +1.2V_GEN_AVDD
* regulator.
*/
pmic_write_reg(bus, 0x12, 0x10, 1);
/*
* Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus.
* First set it to bypass 3.3V straight thru, then enable the regulator
*
* NOTE: We do this early because doing it later seems to hose the CPU
* power rail/partition startup. Need to debug.
*/
pmic_write_reg(bus, 0x16, 0x3f, 1);
/*
* Panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set
* the value (register 0x20 bit 4)
*/
pmic_write_reg(bus, 0x0c, 0x07, 0);
pmic_write_reg(bus, 0x20, 0x10, 1);
}

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src/mainboard/google/nyan_blaze/pmic.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BLAZE_PMIC_H__
#define __MAINBOARD_GOOGLE_NYAN_BLAZE_PMIC_H__
enum {
AS3722_SDO0 = 0,
AS3722_SDO1,
AS3722_SDO2,
AS3722_SDO3,
AS3722_SDO4,
AS3722_SDO5,
AS3722_SDO6,
AS3722_LDO0 = 0x10,
AS3722_LDO1,
AS3722_LDO2,
AS3722_LDO3,
AS3722_LDO4,
AS3722_LDO5,
AS3722_LDO6,
AS3722_LDO7,
AS3722_LDO9 = 0x19,
AS3722_LDO10,
AS3722_LDO11,
};
void pmic_init(unsigned bus);
#endif /* __MAINBOARD_GOOGLE_NYAN_BLAZE_PMIC_H__ */

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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/cache.h>
#include <arch/cpu.h>
#include <arch/exception.h>
#include <arch/stages.h>
#include <device/device.h>
#include <cbfs.h>
#include <cbmem.h>
#include <console/console.h>
#include "sdram_configs.h"
#include "soc/nvidia/tegra124/chip.h"
#include "soc/nvidia/tegra124/sdram.h"
#include <soc/display.h>
#include <timestamp.h>
enum {
L2CTLR_ECC_PARITY = 0x1 << 21,
L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6,
L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6,
L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0,
L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0
};
enum {
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27,
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7,
L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3
};
/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */
static void configure_l2ctlr(void)
{
uint32_t val;
val = read_l2ctlr();
val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK);
val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 |
L2CTLR_ECC_PARITY);
write_l2ctlr(val);
}
/* Configures L2 Auxiliary Control Register for Cortex A15. */
static void configure_l2actlr(void)
{
uint32_t val;
val = read_l2actlr();
val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL |
L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT |
L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE);
write_l2actlr(val);
}
static void __attribute__((noinline)) romstage(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get();
#endif
configure_l2ctlr();
configure_l2actlr();
console_init();
exception_init();
sdram_init(get_sdram_config());
/* used for MMU and CBMEM setup, in MB */
u32 dram_start = (CONFIG_SYS_SDRAM_BASE >> 20);
u32 dram_end = sdram_max_addressable_mb(); /* plus one... */
u32 dram_size = dram_end - dram_start;
mmu_init();
/* Device memory below DRAM is uncached. */
mmu_config_range(0, dram_start, DCACHE_OFF);
/* SRAM is cached. Round the size up to 2MB, the LPAE page size. */
mmu_config_range(0x40000000 >> 20, 2, DCACHE_WRITEBACK);
/* DRAM is cached. */
mmu_config_range(dram_start, dram_size, DCACHE_WRITEBACK);
/* A window for DMA is uncached. */
mmu_config_range(CONFIG_DRAM_DMA_START >> 20,
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
/* The space above DRAM is uncached. */
if (dram_end < 4096)
mmu_config_range(dram_end, 4096 - dram_end, DCACHE_OFF);
mmu_disable_range(0, 1);
dcache_mmu_enable();
/* For quality of the user experience, it's important to get
* the video going ASAP. Because there are long delays in some
* of the powerup steps, we do some very early setup here in
* romstage. The only thing setup_display does is manage
* 4 GPIOs, under control of the config struct members.
* In general, it is safe to enable panel power, and disable
* anything related to the backlight. If we get something wrong,
* we can easily fix it in ramstage by further GPIO manipulation,
* so we feel it is ok to do some setting at this point.
*/
const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0);
printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc);
if (soc && soc->chip_info) {
const struct soc_nvidia_tegra124_config *config =
soc->chip_info;
setup_display((struct soc_nvidia_tegra124_config *)config);
}
cbmem_initialize_empty();
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_init(0);
timestamp_add(TS_START_ROMSTAGE, romstage_start_time);
timestamp_add(TS_START_COPYRAM, timestamp_get());
#endif
void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA,
"fallback/coreboot_ram");
#if CONFIG_COLLECT_TIMESTAMPS
timestamp_add(TS_END_COPYRAM, timestamp_get());
#endif
stage_exit(entry);
}
/* Stub to force arm_init_caches to the top, before any stack/memory accesses */
void main(void)
{
asm volatile ("bl arm_init_caches"
::: "r0","r1","r2","r3","r4","r5","ip");
romstage();
}

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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <soc/nvidia/tegra124/sdram.h>
#include "sdram_configs.h"
static struct sdram_params sdram_configs[] = {
#include "bct/sdram-unused.inc" /* ram_code = 0000 */
#include "bct/sdram-hynix-2GB-792.inc" /* ram_code = 0001 */
#include "bct/sdram-unused.inc" /* ram_code = 0010 */
#include "bct/sdram-unused.inc" /* ram_code = 0011 */
#include "bct/sdram-hynix-4GB-792.inc" /* ram_code = 0100 */
#include "bct/sdram-unused.inc" /* ram_code = 0101 */
#include "bct/sdram-unused.inc" /* ram_code = 0110 */
#include "bct/sdram-unused.inc" /* ram_code = 0111 */
#include "bct/sdram-unused.inc" /* ram_code = 1000 */
#include "bct/sdram-unused.inc" /* ram_code = 1001 */
#include "bct/sdram-unused.inc" /* ram_code = 1010 */
#include "bct/sdram-unused.inc" /* ram_code = 1011 */
#include "bct/sdram-unused.inc" /* ram_code = 1100 */
#include "bct/sdram-unused.inc" /* ram_code = 1101 */
#include "bct/sdram-unused.inc" /* ram_code = 1110 */
#include "bct/sdram-unused.inc" /* ram_code = 1111 */
};
const struct sdram_params *get_sdram_config()
{
uint32_t ramcode = sdram_get_ram_code();
/*
* If we need to apply some special hacks to RAMCODE mapping (ex, by
* board_id), do that now.
*/
printk(BIOS_SPEW, "%s: RAMCODE=%d\n", __func__, ramcode);
if (ramcode >= sizeof(sdram_configs) / sizeof(sdram_configs[0]) ||
sdram_configs[ramcode].MemoryType == NvBootMemoryType_Unused) {
die("Invalid RAMCODE.");
}
return &sdram_configs[ramcode];
}

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/*
* This file is part of the coreboot project.
*
* Copyright 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __MAINBOARD_GOOGLE_NYAN_BLAZE_SDRAM_CONFIG_H__
#define __MAINBOARD_GOOGLE_NYAN_BLAZE_SDRAM_CONFIG_H__
#include <soc/nvidia/tegra124/sdram_param.h>
/* Loads SDRAM configurations for current system. */
const struct sdram_params *get_sdram_config(void);
#endif /* __MAINBOARD_GOOGLE_NYAN_BLAZE_SDRAM_CONFIG_H__ */