From 4e2ffb8812bd91e6f564a05b3e733a55b60a68b5 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Wed, 15 Jul 2009 00:03:28 +0000 Subject: [PATCH] Fix VIA EPIA-M700 target enough for a first serial boot log. Add the respective Super I/O config in Config.lb (Winbond W83697HG), enable COM1 on the board, fix irq_table.c, as well as the PCI devices listed in Config.lb (based on lspci output). This has been tested by Jakob Bornecrantz on hardware, i.e. there is serial output. It does not yet boot to a Linux console successfully, more fixing will be needed. Signed-off-by: Uwe Hermann Acked-by: Jakob Bornecrantz git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/via/epia-m700/Config.lb | 53 +++++++++++++++---- src/mainboard/via/epia-m700/Options.lb | 4 +- .../via/epia-m700/cache_as_ram_auto.c | 9 +++- src/mainboard/via/epia-m700/irq_tables.c | 28 +++++----- 4 files changed, 70 insertions(+), 24 deletions(-) diff --git a/src/mainboard/via/epia-m700/Config.lb b/src/mainboard/via/epia-m700/Config.lb index 636f69ef8e..06eb3d0972 100644 --- a/src/mainboard/via/epia-m700/Config.lb +++ b/src/mainboard/via/epia-m700/Config.lb @@ -109,21 +109,54 @@ config chip.h chip northbridge/via/vx800 # Northbridge device pci_domain 0 on - device pci 0.0 on end # AGP Bridge + device pci 0.0 on end # Host Bridge device pci 0.1 on end # Error Reporting device pci 0.2 on end # Host Bus Control - device pci 0.3 on end # Memory Controller + device pci 0.3 on end # PCI to PCI Bridge device pci 0.4 on end # Power Management - device pci 0.7 on end # V-Link Controller + device pci 0.5 on end # APIC and Central Traffic Control + device pci 0.6 on end # Scratch Registers + device pci 0.7 on end # North-South Module Interface Control device pci 1.0 on end # PCI Bridge - # device pci f.0 on end # IDE/SATA + device pci f.0 on end # IDE/SATA # device pci f.1 on end # IDE - # device pci 10.0 on end # USB 1.1 - # device pci 10.1 on end # USB 1.1 - # device pci 10.2 on end # USB 1.1 - # device pci 10.4 on end # USB 2.0 - # device pci 11.0 on # Southbridge LPC - # end + device pci 10.0 on end # USB 1.1 + device pci 10.1 on end # USB 1.1 + device pci 10.2 on end # USB 1.1 + device pci 10.4 on end # USB 2.0 + device pci 11.0 on # Bus Control and Power Management (SB, LPC) + chip superio/winbond/w83697hf + # TODO: Check all devices, this may need some more work. + device pnp 2e.0 off # Floppy (N/A?) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port (N/A?) + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, GPIO 1 + device pnp 2e.8 off end # MIDI port, GPIO 5 + device pnp 2e.9 off end # GPIO 2-4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM + io 0x60 = 0x290 + end + end + end + device pci 11.7 on end # North-South Module Interface Control + device pci 14.0 on end # HD Audio (Azalia) end device apic_cluster 0 on # APIC cluster chip cpu/via/model_c7 # VIA C7 diff --git a/src/mainboard/via/epia-m700/Options.lb b/src/mainboard/via/epia-m700/Options.lb index 881471eee2..b04013a9da 100644 --- a/src/mainboard/via/epia-m700/Options.lb +++ b/src/mainboard/via/epia-m700/Options.lb @@ -120,7 +120,7 @@ default CONFIG_UDELAY_TSC = 1 default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1 default CONFIG_HAVE_HARD_RESET = 0 default CONFIG_HAVE_PIRQ_TABLE = 0 -default CONFIG_IRQ_SLOT_COUNT = 14 +default CONFIG_IRQ_SLOT_COUNT = 13 default CONFIG_HAVE_ACPI_TABLES = 1 default CONFIG_HAVE_OPTION_TABLE = 1 default CONFIG_ROM_IMAGE_SIZE = 128 * 1024 @@ -135,6 +135,8 @@ default CONFIG_ROM_PAYLOAD = 1 default CONFIG_CROSS_COMPILE = "" default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32" default HOSTCC = "gcc" +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9 default CONFIG_CBFS = 0 ## diff --git a/src/mainboard/via/epia-m700/cache_as_ram_auto.c b/src/mainboard/via/epia-m700/cache_as_ram_auto.c index b0d543b01d..daa4be85bf 100644 --- a/src/mainboard/via/epia-m700/cache_as_ram_auto.c +++ b/src/mainboard/via/epia-m700/cache_as_ram_auto.c @@ -55,6 +55,10 @@ #include "cpu/x86/car/copy_and_run.c" #include "wakeup.h" +#include "superio/winbond/w83697hf/w83697hf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) + /* * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. @@ -407,7 +411,10 @@ void amd64_main(unsigned long bist) * console_init()) are the same with epia-cn port. */ pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); - EmbedComInit(); + /* EmbedComInit(); */ + w83697hf_set_clksel_48(SERIAL_DEV); + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); /* enable_vx800_serial(); */ /* uart_init(); */ diff --git a/src/mainboard/via/epia-m700/irq_tables.c b/src/mainboard/via/epia-m700/irq_tables.c index 817b4d6130..3e4b47ebe3 100644 --- a/src/mainboard/via/epia-m700/irq_tables.c +++ b/src/mainboard/via/epia-m700/irq_tables.c @@ -26,23 +26,27 @@ const struct irq_routing_table intel_irq_routing_table = { 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ 0x00, /* Where the interrupt router lies (bus) */ (0x11 << 3) | 0x0, /* Where the interrupt router lies (dev) */ - 0xc20, /* IRQs devoted exclusively to PCI usage */ + 0xca0, /* IRQs devoted exclusively to PCI usage */ 0x1106, /* Vendor */ - 0x8409, /* Device */ + 0x596, /* Device */ 0, /* Miniport */ {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ - 0xc6, /* Checksum. 0xa0? */ + 0xdb, /* Checksum. 0xa0? */ { /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x08 << 3) | 0x0, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, - {0x00, (0x0b << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x0c << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x0d << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x0e << 3) | 0x0, {{0x03, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x0f << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0x0deb8}}, 0x0, 0x0}, - {0x00, (0x14 << 3) | 0x0, {{0x02, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x1, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x2, 0x0}, + {0x00, (0x03 << 3) | 0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x3, 0x0}, + {0x04, (0x04 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}}, 0x4, 0x0}, + {0x04, (0x0e << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x5, 0x0}, + {0x00, (0x11 << 3) | 0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x0f << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x10 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x02 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x0, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x03 << 3) | 0x1, {{0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}, {0x09, 0xdeb8}}, 0x0, 0x0}, + {0x00, (0x14 << 3) | 0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}}, 0x0, 0x0}, } };