Should be part of 6044. I forgot to add the directory :/
This adds the m2v directory and necessary files to src/mainboards/asus and adjusts the Kconfig. Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6045 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Tobias Diedrich
Rudolf Marek
parent
4a6dfebf39
commit
4e6305f4ab
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@ -0,0 +1,77 @@
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if BOARD_ASUS_M2V
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select ARCH_X86
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select CPU_AMD_SOCKET_AM2
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select DIMM_DDR2
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select QRANK_DIMM_SUPPORT
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select HAVE_OPTION_TABLE
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select K8_HT_FREQ_1G_SUPPORT
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select NORTHBRIDGE_AMD_AMDK8
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select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX
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select SOUTHBRIDGE_VIA_VT8237R
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select SOUTHBRIDGE_VIA_K8T890
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select SUPERIO_ITE_IT8712F
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select CACHE_AS_RAM
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select BOARD_ROMSIZE_KB_512
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select RAMINIT_SYSINFO
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select TINY_BOOTBLOCK
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config MAINBOARD_DIR
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string
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default asus/m2v
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config DCACHE_RAM_BASE
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hex
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default 0xcc000
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config DCACHE_RAM_SIZE
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hex
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default 0x4000
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x1000
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config APIC_ID_OFFSET
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hex
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default 0x10
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config SB_HT_CHAIN_ON_BUS0
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int
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default 1
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config MAINBOARD_PART_NUMBER
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string
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default "M2V"
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config HW_MEM_HOLE_SIZEK
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hex
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default 0
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config MAX_CPUS
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int
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default 2
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config HEAP_SIZE
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hex
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default 0x40000
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config HT_CHAIN_END_UNITID_BASE
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hex
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default 0x20
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config HT_CHAIN_UNITID_BASE
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hex
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default 0x0
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x1043
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endif # BOARD_ASUS_M2V
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,98 @@
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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#96 288 r 0 temporary_filler
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0 384 r 0 reserved_memory
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 1 hw_scrubber
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396 1 e 1 interleave_chip_selects
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397 2 e 8 max_mem_clock
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399 1 e 2 multi_core
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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420 4 e 7 boot_second
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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445 1 e 1 iommu
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 amd_reserved
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Network
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7 1 HDD
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7 2 Floppy
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7 8 Fallback_Network
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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8 0 DDR400
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8 1 DDR333
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8 2 DDR266
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8 3 DDR200
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9 0 off
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9 1 87.5%
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9 2 75.0%
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9 3 62.5%
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9 4 50.0%
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9 5 37.5%
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9 6 25.0%
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9 7 12.5%
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checksums
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checksum 392 983 984
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@ -0,0 +1,74 @@
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chip northbridge/amd/amdk8/root_complex # Root complex
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device lapic_cluster 0 on # APIC cluster
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chip cpu/amd/socket_AM2 # CPU
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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chip northbridge/amd/amdk8 # mc0
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device pci 18.0 on # Northbridge
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# Devices on link 0, link 0 == LDT 0
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chip southbridge/via/vt8237r # Southbridge
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register "ide0_enable" = "1" # Enable IDE channel 0
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register "ide1_enable" = "1" # Enable IDE channel 1
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register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0
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register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1
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register "fn_ctrl_lo" = "0xc0" # Enable SB functions
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register "fn_ctrl_hi" = "0x0d" # Enable SB functions
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device pci 0.0 on end # HT
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device pci f.1 on end # IDE
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device pci 11.0 on # LPC
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chip drivers/generic/generic # DIMM 0-0-0
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device i2c 50 on end
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end
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chip drivers/generic/generic # DIMM 0-0-1
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device i2c 51 on end
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end
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chip drivers/generic/generic # DIMM 0-1-0
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device i2c 52 on end
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end
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chip drivers/generic/generic # DIMM 0-1-1
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device i2c 53 on end
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end
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chip superio/ite/it8712f # Super I/O
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device pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 off end # Com2 (N/A on this board)
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device pnp 2e.3 on # Lpt1
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 3
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end
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device pnp 2e.4 on # Environment controller
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io 0x60 = 0xd00
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io 0x62 = 0xc00
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irq 0x70 = 0x00
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end
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device pnp 2e.5 off end # PS/2 keyboard
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device pnp 2e.6 off end # PS/2 mouse
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device pnp 2e.7 off end # GPIO config
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device pnp 2e.8 off end # Midi port
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device pnp 2e.9 off end # Game port
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device pnp 2e.a off end # IR
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end
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end
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device pci 12.0 off end # VIA LAN (off, other chip used)
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device pci 13.0 on end # br
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device pci 13.1 on end # br2, need to have it here to discover it
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end
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chip southbridge/via/k8t890 # "Southbridge" K8T890
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end
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end
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device pci 18.1 on end
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device pci 18.2 on end
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device pci 18.3 on end
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end
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end
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end
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@ -0,0 +1,25 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include "chip.h"
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struct chip_operations mainboard_ops = {
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CHIP_NAME("ASUS M2V")
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};
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@ -0,0 +1,299 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2006 AMD
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* (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
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* Copyright (C) 2006 MSI
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* (Written by Bingxun Shi <bingxunshi@gmail.com> for MSI)
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* Copyright (C) 2008 Rudolf Marek <r.marek@assembler.cz>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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unsigned int get_sbdn(unsigned bus);
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/* Used by init_cpus and fidvid */
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#define SET_FIDVID 1
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/* If we want to wait for core1 done before DQS training, set it to 0. */
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#define SET_FIDVID_CORE0_ONLY 1
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#if CONFIG_K8_REV_F_SUPPORT == 1
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#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
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#endif
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#include <stdint.h>
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#include <string.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/x86/lapic.h>
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#include <pc80/mc146818rtc.h>
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#include <console/console.h>
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#include <cpu/amd/model_fxx_rev.h>
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/amd/model_fxx/apic_timer.c"
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#include "lib/delay.c"
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "superio/ite/it8712f/it8712f_early_serial.c"
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#include "southbridge/via/vt8237r/vt8237r_early_smbus.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "northbridge/amd/amdk8/setup_resource_map.c"
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#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
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#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
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#define IT8712F_GPIO_BASE 0x0a20
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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static void activate_spd_rom(const struct mem_controller *ctrl)
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{
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}
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// defines S3_NVRAM_EARLY:
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#include "southbridge/via/k8t890/k8t890_early_car.c"
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#include "northbridge/amd/amdk8/amdk8.h"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "northbridge/amd/amdk8/raminit_f.c"
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#include "lib/generic_sdram.c"
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#include "cpu/amd/dualcore/dualcore.c"
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#include "cpu/amd/car/post_cache_as_ram.c"
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#include "cpu/amd/model_fxx/init_cpus.c"
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#include "cpu/amd/model_fxx/fidvid.c"
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#include "northbridge/amd/amdk8/resourcemap.c"
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void soft_reset(void)
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{
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uint8_t tmp;
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set_bios_reset();
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print_debug("soft reset\n");
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/* PCI reset */
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tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
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tmp |= 0x01;
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/* FIXME from S3 set bit1 to disable USB reset VT8237A/S */
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pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp);
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while (1) {
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/* daisy daisy ... */
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hlt();
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}
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}
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unsigned int get_sbdn(unsigned bus)
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{
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device_t dev;
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dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
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PCI_DEVICE_ID_VIA_VT8237R_LPC), bus);
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return (dev >> 15) & 0x1f;
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}
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struct gpio_init_val {
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u8 addr;
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u8 val;
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};
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static const struct gpio_init_val gpio_init_data[] = {
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/* multi-function pin selection */
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{ 0x25, 0x00 },
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{ 0x28, 0x00 }, /* gp46 is infrared receive input */
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{ 0x29, 0x40 }, /* reserved value?!? */
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{ 0x2a, 0x00 },
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{ 0x2c, 0x1d }, /* pin91 is VIN7 instead of PCIRSTIN# */
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/* gpio i/o port base */
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{ 0x62, IT8712F_GPIO_BASE >> 8 },
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{ 0x63, IT8712F_GPIO_BASE & 0xff },
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/* 0xb8 - 0xbc: gpio pull-up enable */
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{ 0xb8, 0x00 },
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/* 0xc0 - 0xc4: gpio alternate function select */
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{ 0xc0, 0x00 },
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{ 0xc3, 0x00 },
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{ 0xc4, 0xc0 },
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/* 0xc8 - 0xcc: gpio output enable */
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{ 0xc8, 0x00 },
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{ 0xcb, 0x00 },
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{ 0xcc, 0xc0 },
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/* end of list */
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{ 0, 0 },
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};
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static void m2v_it8712f_gpio_init(void)
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{
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const struct gpio_init_val *giv;
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printk(BIOS_SPEW, "it8712f gpio init...\n");
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/*
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* it8712f gpio config
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*
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* Most importantly this switches pin 91 from
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* PCIRSTIN# to VIN7.
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* Note that only PCIRST3# and PCIRST5# are affected
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* by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always
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* direct buffers of #LRESET (low pin count bus reset).
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||||
* If this is not done All PCIRST are in reset state and the
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* pcie slots don't initialize.
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*
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* pci reset handling:
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* pin 91: VIN7 (alternate PCIRSTIN#)
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* pin 48: PCIRST5# / gpio port 5 bit 0
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* pin 84: PCIRST4# / gpio port 1 bit 0
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* pin 31: PCIRST1# / gpio port 1 bit 4
|
||||
* pin 33: PCIRST2# / gpio port 1 bit 2
|
||||
* pin 34: PCIRST3# / gpio port 1 bit 1
|
||||
*
|
||||
* PCIRST[0-5]# are connected as follows:
|
||||
* pcirst1# -> pci bus
|
||||
* pcirst2# -> ide bus
|
||||
* pcirst3# -> pcie devices
|
||||
* pcirst4# -> pcie graphics
|
||||
* pcirst5# -> maybe n/c (untested)
|
||||
*
|
||||
* For software control of PCIRST[1-5]#:
|
||||
* 0x2a=0x17 (deselect pcirst# hardwiring, enable 0x25 control)
|
||||
* 0x25=0x17 (select gpio function)
|
||||
* 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable
|
||||
* 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable
|
||||
*/
|
||||
it8712f_enter_conf();
|
||||
giv = gpio_init_data;
|
||||
while (giv->addr) {
|
||||
printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n",
|
||||
giv->addr, giv->val);
|
||||
it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val);
|
||||
giv++;
|
||||
}
|
||||
it8712f_exit_conf();
|
||||
}
|
||||
|
||||
static void m2v_bus_init(void)
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
printk(BIOS_SPEW, "m2v_bus_init\n");
|
||||
|
||||
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
|
||||
PCI_DEVICE_ID_VIA_K8T890CF_0), 0);
|
||||
pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
|
||||
|
||||
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
|
||||
PCI_DEVICE_ID_VIA_K8T890CF_5), 0);
|
||||
/*
|
||||
* bit | meaning
|
||||
* 6 | 0: hide scratch register function 0:0.6 (we don't use it)
|
||||
* 5 | 1: enable pcie bridge 0:2.0
|
||||
* 4 | 0: hide pcie bridge 0:3.3 (not connected)
|
||||
* 3 | 1: enable pcie bridge 0:3.2
|
||||
* 2 | 1: enable pcie bridge 0:3.1
|
||||
* 1 | 1: enable pcie bridge 0:3.0
|
||||
*/
|
||||
pci_write_config8(dev, 0xf0, 0x2e);
|
||||
}
|
||||
|
||||
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
|
||||
{
|
||||
static const uint16_t spd_addr[] = {
|
||||
// Node 0
|
||||
(0xa << 3) | 0, (0xa << 3) | 2, 0, 0,
|
||||
(0xa << 3) | 1, (0xa << 3) | 3, 0, 0,
|
||||
// Node 1
|
||||
(0xa << 3) | 4, (0xa << 3) | 6, 0, 0,
|
||||
(0xa << 3) | 5, (0xa << 3) | 7, 0, 0,
|
||||
};
|
||||
unsigned bsp_apicid = 0;
|
||||
int needs_reset = 0;
|
||||
struct sys_info *sysinfo =
|
||||
(struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
|
||||
|
||||
it8712f_24mhz_clkin();
|
||||
it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
it8712f_kill_watchdog();
|
||||
uart_init();
|
||||
console_init();
|
||||
enable_rom_decode();
|
||||
m2v_bus_init();
|
||||
m2v_it8712f_gpio_init();
|
||||
|
||||
printk(BIOS_INFO, "now booting... \n");
|
||||
|
||||
if (bist == 0)
|
||||
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
|
||||
|
||||
/* Halt if there was a built in self test failure. */
|
||||
report_bist_failure(bist);
|
||||
setup_default_resource_map();
|
||||
setup_coherent_ht_domain();
|
||||
wait_all_core0_started();
|
||||
|
||||
printk(BIOS_INFO, "now booting... All core 0 started\n");
|
||||
|
||||
#if CONFIG_LOGICAL_CPUS==1
|
||||
/* It is said that we should start core1 after all core0 launched. */
|
||||
start_other_cores();
|
||||
wait_all_other_cores_started(bsp_apicid);
|
||||
#endif
|
||||
init_timer();
|
||||
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
|
||||
|
||||
needs_reset = optimize_link_coherent_ht();
|
||||
print_debug_hex8(needs_reset);
|
||||
needs_reset |= optimize_link_incoherent_ht(sysinfo);
|
||||
print_debug_hex8(needs_reset);
|
||||
needs_reset |= k8t890_early_setup_ht();
|
||||
print_debug_hex8(needs_reset);
|
||||
|
||||
if (needs_reset) {
|
||||
printk(BIOS_DEBUG, "ht reset -\n");
|
||||
soft_reset();
|
||||
printk(BIOS_DEBUG, "FAILED!\n");
|
||||
}
|
||||
|
||||
/* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */
|
||||
/* allow LDT STOP asserts */
|
||||
vt8237_sb_enable_fid_vid();
|
||||
|
||||
enable_fid_change();
|
||||
print_debug("after enable_fid_change\n");
|
||||
|
||||
init_fidvid_bsp(bsp_apicid);
|
||||
|
||||
/* Stop the APs so we can start them later in init. */
|
||||
allow_all_aps_stop(bsp_apicid);
|
||||
|
||||
/* It's the time to set ctrl now. */
|
||||
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
|
||||
enable_smbus();
|
||||
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
|
||||
post_cache_as_ram();
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue