mb/google/brya/var/brya0: add HPS as generic I2C peripheral

Some brya0 units have HPS fitted and connected to PCH I2C2, rather than
a user-facing camera.

Because HPS uses I2C address 0x51, which may conflict with the
user-facing camera EEPROM, introduce a new fw_config bit to indicate
whether HPS is present.

BUG=b:202784200
TEST=FW_NAME=brya0 emerge-brya coreboot chromeos-bootimage
TEST=ectool cbi set 6 0x28191 4  # set bit 17 for HPS
TEST=flashrom -p internal -w image-brya0.serial.bin

Signed-off-by: Dan Callaghan <dcallagh@google.com>
Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58646
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Dan Callaghan 2021-10-28 21:22:22 +11:00 committed by Patrick Georgi
parent 2a83085a06
commit 4e6c915fcc
1 changed files with 18 additions and 0 deletions

View File

@ -27,6 +27,11 @@ fw_config
option UFC_USB 0 option UFC_USB 0
option UFC_MIPI_IMX208 1 option UFC_MIPI_IMX208 1
end end
# Bits 15 and 16 were intended for WFC but never declared here
field HPS 17 17
option HPS_ABSENT 0
option HPS_PRESENT 1
end
end end
chip soc/intel/alderlake chip soc/intel/alderlake
@ -532,6 +537,19 @@ chip soc/intel/alderlake
probe UFC UFC_MIPI_IMX208 probe UFC UFC_MIPI_IMX208
end end
end end
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
register "desc" = ""Chrome OS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
# The address we provide here is not significant because
# neither coreboot nor Linux have a driver for HPS,
# it's only used from userspace.
device i2c 30 on
probe HPS HPS_PRESENT
end
end
end end
device ref i2c3 on end device ref i2c3 on end
device ref i2c5 on device ref i2c5 on