mb/google/brya/var/brya0: add HPS as generic I2C peripheral
Some brya0 units have HPS fitted and connected to PCH I2C2, rather than a user-facing camera. Because HPS uses I2C address 0x51, which may conflict with the user-facing camera EEPROM, introduce a new fw_config bit to indicate whether HPS is present. BUG=b:202784200 TEST=FW_NAME=brya0 emerge-brya coreboot chromeos-bootimage TEST=ectool cbi set 6 0x28191 4 # set bit 17 for HPS TEST=flashrom -p internal -w image-brya0.serial.bin Signed-off-by: Dan Callaghan <dcallagh@google.com> Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58646 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -27,6 +27,11 @@ fw_config
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option UFC_USB 0
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option UFC_USB 0
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option UFC_MIPI_IMX208 1
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option UFC_MIPI_IMX208 1
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end
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end
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# Bits 15 and 16 were intended for WFC but never declared here
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field HPS 17 17
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option HPS_ABSENT 0
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option HPS_PRESENT 1
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end
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end
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end
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chip soc/intel/alderlake
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chip soc/intel/alderlake
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@ -532,6 +537,19 @@ chip soc/intel/alderlake
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probe UFC UFC_MIPI_IMX208
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probe UFC UFC_MIPI_IMX208
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end
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end
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end
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end
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chip drivers/i2c/generic
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register "hid" = ""GOOG0020""
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register "desc" = ""Chrome OS HPS""
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
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# HPS uses I2C addresses 0x30 and 0x51.
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# The address we provide here is not significant because
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# neither coreboot nor Linux have a driver for HPS,
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# it's only used from userspace.
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device i2c 30 on
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probe HPS HPS_PRESENT
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end
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end
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end
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end
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device ref i2c3 on end
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device ref i2c3 on end
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device ref i2c5 on
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device ref i2c5 on
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