soc/amd/*/chip: factor out FSP-S call

Move the call into the FSP code to a file in the common AMD FSP code to
isolate the FSP-specific parts of the code.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic8236db7ac80275a65020b7e7a9acce8314c831c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>

src/soc/amd/cezanne/chip.c

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/data_fabric.h>
+#include <amdblocks/fsp.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp/api.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/pci_devs.h>
@@ -37,7 +37,7 @@ static void soc_init(void *chip_info)
 {
 	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
 
-	fsp_silicon_init();
+	amd_fsp_silicon_init();
 
 	data_fabric_set_mmio_np();
 

src/soc/amd/common/block/include/amdblocks/fsp.h

@@ -4,5 +4,6 @@
 #define AMD_BLOCK_FSP_H
 
 void amd_fsp_early_init(void);
+void amd_fsp_silicon_init(void);
 
 #endif /* AMD_BLOCK_FSP_H */

src/soc/amd/common/fsp/Makefile.inc

@@ -6,6 +6,7 @@ romstage-y += fsp_romstage.c
 romstage-y += fsp_validate.c
 ramstage-y += fsp_graphics.c
 ramstage-y += fsp_memmap.c
+ramstage-y += fsp_ramstage.c
 ramstage-y += fsp_report_resources.c
 ramstage-y += fsp_reset.c
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fsp-acpi.c

src/soc/amd/common/fsp/fsp_ramstage.c

@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/fsp.h>
+#include <fsp/api.h>
+
+void amd_fsp_silicon_init(void)
+{
+	fsp_silicon_init();
+}

src/soc/amd/glinda/chip.c

@@ -3,10 +3,10 @@
 /* TODO: Update for Glinda */
 
 #include <amdblocks/data_fabric.h>
+#include <amdblocks/fsp.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp/api.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/pci_devs.h>
@@ -39,7 +39,7 @@ static void soc_init(void *chip_info)
 {
 	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
 
-	fsp_silicon_init();
+	amd_fsp_silicon_init();
 
 	data_fabric_set_mmio_np();
 

src/soc/amd/mendocino/chip.c

@@ -1,10 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/data_fabric.h>
+#include <amdblocks/fsp.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp/api.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/pci_devs.h>
@@ -37,7 +37,7 @@ static void soc_init(void *chip_info)
 {
 	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
 
-	fsp_silicon_init();
+	amd_fsp_silicon_init();
 
 	data_fabric_set_mmio_np();
 

src/soc/amd/phoenix/chip.c

@@ -3,10 +3,10 @@
 /* TODO: Update for Phoenix */
 
 #include <amdblocks/data_fabric.h>
+#include <amdblocks/fsp.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <fsp/api.h>
 #include <soc/acpi.h>
 #include <soc/cpu.h>
 #include <soc/pci_devs.h>
@@ -39,7 +39,7 @@ static void soc_init(void *chip_info)
 {
 	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
 
-	fsp_silicon_init();
+	amd_fsp_silicon_init();
 
 	data_fabric_set_mmio_np();
 

src/soc/amd/picasso/chip.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/data_fabric.h>
+#include <amdblocks/fsp.h>
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -11,7 +12,6 @@
 #include <soc/pci_devs.h>
 #include <soc/southbridge.h>
 #include "chip.h"
-#include <fsp/api.h>
 
 static const char *soc_acpi_name(const struct device *dev)
 {
@@ -38,7 +38,7 @@ static void soc_init(void *chip_info)
 {
 	default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables;
 
-	fsp_silicon_init();
+	amd_fsp_silicon_init();
 
 	data_fabric_set_mmio_np();
 	fch_init(chip_info);