qualcomm/sc7280: Add support for edp and mdp driver
- Add support for edp aux read and write.
- Update edp panel properties based on edid read.
- Configure edp controller and edp phy.
Panel details:
Manufacturer: SHP Model 1523 Serial Number 0
Made week 53 of 2020
EDID version: 1.4
Digital display
8 bits per primary color channel
DisplayPort interface
Maximum image size: 31 cm x 17 cm
Gamma: 220%
Check DPMS levels
Supported color formats: RGB 4:4:4
Default (sRGB) color space is primary color space
First detailed timing is preferred timing
Supports GTF timings within operating range
Established timings supported:
Standard timings supported:
Detailed timings
Hex of detail: 5a8780a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 346500 KHz, 135 mm x ae mm
0780 07b0 07d0 0820 hborder 0
0438 043b 0440 0485 vborder 0
-hsync -vsync
Did detailed timing
Hex of detail: 653880a070384d403020350035ae10000018
Detailed mode (IN HEX): Clock 144370 KHz, 135 mm x ae mm
0780 07b0 07d0 0820 hborder 0
0438 043b 0440 0485 vborder 0
-hsync -vsync
Hex of detail: 000000fd003090a7a7230100000000000000
Monitor ranges (bare limits): 48-144Hz V, 167-167kHz H, max dotclock
350MHz
Hex of detail: 000000fc004c513134304d314a5734390a20
Monitor name: LQ140M1JW49
Changes in V2:
- Remove Misc delays in edp code.
- Move mdss soc code to disp.c
- Update EDID read using I2C write & read.
Changes in V3:
- Remove unrelated delays.
- Misc changes.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Change-Id: If89abb76028766b19450e756889a5d7776106f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This commit is contained in:
Vinod Polimera
Shelley Chen
parent
7528311929
commit
4e93e94c7c
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@ -14,6 +14,9 @@ config SOC_QUALCOMM_SC7280
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select SOC_QUALCOMM_COMMON
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select CACHE_MRC_SETTINGS
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select HAS_RECOVERY_MRC_CACHE
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_FORCE_NATIVE_VGA_INIT
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select HAVE_LINEAR_FRAMEBUFFER
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select COMPRESS_BOOTBLOCK
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select HAVE_UART_SPECIAL
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select PCI
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@ -46,6 +46,11 @@ ramstage-y += ../common/usb/snps_usb_phy.c
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ramstage-y += ../common/usb/qmpv4_usb_phy.c
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ramstage-y += ../common/aop_load_reset.c
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ramstage-y += cpucp_load_reset.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/edp_aux.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/edp_ctrl.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/edp_phy_7nm.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/display/mdss.c
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ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display/disp.c
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ramstage-$(CONFIG_PCI) += ../common/pcie_common.c
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ramstage-$(CONFIG_PCI) += pcie.c
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@ -0,0 +1,60 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/mmio.h>
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#include <soc/clock.h>
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#include <soc/display/mdssreg.h>
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void enable_mdss_clk(void)
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{
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mdss_clock_enable(GCC_DISP_AHB);
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// enable gdsc before enabling clocks.
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clock_enable_gdsc(MDSS_CORE_GDSC);
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mdss_clock_enable(GCC_DISP_HF_AXI);
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mdss_clock_enable(GCC_DISP_SF_AXI);
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mdss_clock_enable(MDSS_CLK_AHB);
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mdss_clock_configure(MDSS_CLK_MDP, 400 * MHz, 0, 0, 0, 0, 0);
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mdss_clock_enable(MDSS_CLK_MDP);
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mdss_clock_configure(MDSS_CLK_VSYNC, 0, 0, 0, 0, 0, 0);
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mdss_clock_enable(MDSS_CLK_VSYNC);
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}
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void mdss_intf_tg_setup(struct edid *edid)
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{
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uint32_t hsync_period, vsync_period;
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uint32_t active_vstart, active_vend, active_hctl;
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uint32_t display_hctl, hsync_ctl, display_vstart, display_vend;
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hsync_period = edid->mode.ha + edid->mode.hbl;
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vsync_period = edid->mode.va + edid->mode.vbl;
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display_vstart = edid->mode.vbl * hsync_period + edid->mode.hbl;
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display_vend = (vsync_period * hsync_period) - 1;
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hsync_ctl = (hsync_period << 16) | edid->mode.hspw;
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display_hctl = edid->mode.hbl | (hsync_period - 1) << 16;
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active_vstart = edid->mode.vbl * hsync_period;
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active_vend = display_vend;
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active_hctl = display_hctl;
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write32(&mdp_intf->intf_active_v_start_f0, active_vstart);
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write32(&mdp_intf->intf_active_v_end_f0, active_vend);
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write32(&mdp_intf->intf_active_hctl, active_hctl);
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write32(&mdp_intf->display_data_hctl, display_hctl);
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write32(&mdp_intf->intf_hsync_ctl, hsync_ctl);
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write32(&mdp_intf->intf_vysnc_period_f0, vsync_period * hsync_period);
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write32(&mdp_intf->intf_vysnc_pulse_width_f0, edid->mode.vspw * hsync_period);
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write32(&mdp_intf->intf_disp_hctl, display_hctl);
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write32(&mdp_intf->intf_disp_v_start_f0, display_vstart);
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write32(&mdp_intf->intf_disp_v_end_f0, display_vend);
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write32(&mdp_intf->intf_underflow_color, 0x00);
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}
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void mdss_ctrl_config(void)
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{
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/* Select vigo pipe active */
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write32(&mdp_ctl->ctl_fetch_pipe_active, FETCH_PIPE_VIG0_ACTIVE);
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/* PPB0 to INTF1 */
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write32(&mdp_ctl->ctl_intf_active, INTF_ACTIVE_5);
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}
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@ -0,0 +1,229 @@
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// SPDX-License-Identifier: GPL-2.0-only
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#include <device/mmio.h>
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#include <console/console.h>
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#include <edid.h>
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#include <delay.h>
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#include <timer.h>
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#include <types.h>
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#include <string.h>
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#include <soc/display/edp_aux.h>
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#include <soc/display/edp_reg.h>
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#define AUX_CMD_FIFO_LEN 144
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#define AUX_CMD_NATIVE_MAX 16
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#define AUX_CMD_I2C_MAX 128
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#define AUX_INTR_I2C_DONE BIT(0)
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#define AUX_INTR_WRONG_ADDR BIT(1)
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#define AUX_INTR_CONSECUTIVE_TIMEOUT BIT(2)
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#define AUX_INTR_CONSECUTIVE_NACK_DEFER BIT(3)
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#define AUX_INTR_WRONG_RD_DATA_CNT BIT(4)
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#define AUX_INTR_NACK_I2C BIT(5)
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#define AUX_INTR_DEFER_I2C BIT(6)
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#define AUX_INTR_DPPHY_AUX_ERR BIT(7)
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#define EDP_AUX_INTERRUPT (AUX_INTR_I2C_DONE | AUX_INTR_WRONG_ADDR | \
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AUX_INTR_CONSECUTIVE_TIMEOUT | \
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AUX_INTR_CONSECUTIVE_NACK_DEFER | \
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AUX_INTR_WRONG_RD_DATA_CNT | AUX_INTR_DEFER_I2C | \
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AUX_INTR_NACK_I2C | AUX_INTR_DPPHY_AUX_ERR)
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static void edp_wait_for_aux_done(void)
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{
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u32 intr_status = 0;
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if (!wait_ms(100, read32(&edp_auxclk->status) & EDP_AUX_INTERRUPT)) {
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printk(BIOS_ERR, "ERROR: AUX SEND not acknowledged\n");
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return;
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}
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intr_status = read32(&edp_auxclk->status);
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if (!(intr_status & AUX_INTR_I2C_DONE)) {
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printk(BIOS_ERR, "ERROR: AUX command failed, status = %#x\n", intr_status);
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return;
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}
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write32(&edp_ahbclk->interrupt_status, 0x0);
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}
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static int edp_msg_fifo_tx(unsigned int address, u8 request, void *buffer, size_t size)
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{
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u32 data[4];
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u32 reg, len;
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bool native = (request == DP_AUX_NATIVE_WRITE) || (request == DP_AUX_NATIVE_READ);
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bool read = (request == DP_AUX_I2C_READ) || (request == DP_AUX_NATIVE_READ);
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u8 *msgdata = buffer;
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int i;
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if (read)
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len = 4;
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else
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len = size + 4;
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/*
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* cmd fifo only has depth of 144 bytes
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*/
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if (len > AUX_CMD_FIFO_LEN)
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return -1;
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/* Pack cmd and write to HW */
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data[0] = (address >> 16) & 0xf; /* addr[19:16] */
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if (read)
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data[0] |= AUX_CMD_READ; /* R/W */
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data[1] = (address >> 8) & 0xff; /* addr[15:8] */
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data[2] = address & 0xff; /* addr[7:0] */
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data[3] = (size - 1) & 0xff; /* len[7:0] */
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for (i = 0; i < len; i++) {
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reg = (i < 4) ? data[i] : msgdata[i - 4];
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reg = EDP_AUX_DATA_DATA(reg); /* index = 0, write */
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if (i == 0)
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reg |= EDP_AUX_DATA_INDEX_WRITE;
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write32(&edp_auxclk->aux_data, reg);
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}
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/* clear old aux transaction control */
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write32(&edp_auxclk->aux_trans_ctrl, 0);
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reg = RX_STOP_ERR | RX_DEC_ERR | RX_SYNC_ERR | RX_ALIGN_ERR | TX_REQ_ERR;
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write32(&edp_phy->aux_interrupt_clr, reg);
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write32(&edp_phy->aux_interrupt_clr, reg | GLOBE_REQ_CLR);
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write32(&edp_phy->aux_interrupt_clr, 0x0);
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reg = 0; /* Transaction number is always 1 */
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if (!native) /* i2c */
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reg |= EDP_AUX_TRANS_CTRL_I2C | EDP_AUX_TRANS_CTRL_NO_SEND_ADDR |
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EDP_AUX_TRANS_CTRL_NO_SEND_STOP;
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reg |= EDP_AUX_TRANS_CTRL_GO;
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write32(&edp_auxclk->aux_trans_ctrl, reg);
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edp_wait_for_aux_done();
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return 0;
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}
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static int edp_msg_fifo_rx(void *buffer, size_t size)
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{
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u32 data;
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u8 *dp;
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int i;
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u32 len = size;
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clrbits32(&edp_auxclk->aux_trans_ctrl, EDP_AUX_TRANS_CTRL_GO);
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write32(&edp_auxclk->aux_data,
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EDP_AUX_DATA_INDEX_WRITE | EDP_AUX_DATA_READ); /* index = 0 */
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dp = buffer;
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/* discard first byte */
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data = read32(&edp_auxclk->aux_data);
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for (i = 0; i < len; i++) {
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data = read32(&edp_auxclk->aux_data);
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dp[i] = (u8)((data >> 8) & 0xff);
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}
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return 0;
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}
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ssize_t edp_aux_transfer(unsigned int address, u8 request, void *buffer, size_t size)
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{
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ssize_t ret;
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bool native = (request == DP_AUX_NATIVE_WRITE) || (request == DP_AUX_NATIVE_READ);
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bool read = (request == DP_AUX_I2C_READ) || (request == DP_AUX_NATIVE_READ);
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/* Ignore address only message */
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if ((size == 0) || (buffer == NULL)) {
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printk(BIOS_ERR, "%s: invalid size or buffer\n", __func__);
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return size;
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}
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/* msg sanity check */
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if ((native && (size > AUX_CMD_NATIVE_MAX)) ||
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(size > AUX_CMD_I2C_MAX)) {
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printk(BIOS_ERR, "%s: invalid msg: size(%zu), request(%x)\n",
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__func__, size, request);
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return -1;
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}
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ret = edp_msg_fifo_tx(address, request, buffer, size);
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if (ret < 0) {
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printk(BIOS_ERR, "edp aux transfer tx failed\n");
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return ret;
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}
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if (read) {
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ret = edp_msg_fifo_rx(buffer, size);
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if (ret < 0) {
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printk(BIOS_ERR, "edp aux transfer rx failed\n");
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return ret;
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}
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}
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/* Return requested size for success or retry */
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ret = size;
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return ret;
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}
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int edp_read_edid(struct edid *out)
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{
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int err;
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u8 edid[EDID_LENGTH * 2];
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int edid_size = EDID_LENGTH;
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uint8_t reg_addr = 0;
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err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_WRITE, ®_addr, 1);
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if (err > 0)
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err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_READ, edid, EDID_LENGTH);
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if (err < EDID_LENGTH) {
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printk(BIOS_ERR, "ERROR: Failed to read EDID. :%d\n", err);
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return err;
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}
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if (edid[EDID_EXTENSION_FLAG]) {
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printk(BIOS_ERR, " read EDID ext block.\n");
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edid_size += EDID_LENGTH;
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reg_addr = EDID_LENGTH;
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err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_WRITE, ®_addr, 1);
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if (err > 0)
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err = edp_aux_transfer(EDID_I2C_ADDR, DP_AUX_I2C_READ,
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&edid[EDID_LENGTH], EDID_LENGTH);
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if (err < EDID_LENGTH) {
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printk(BIOS_ERR, "Failed to read EDID ext block.\n");
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return err;
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}
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}
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if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) {
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printk(BIOS_ERR, "ERROR: Failed to decode EDID.\n");
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return CB_ERR;
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}
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return CB_SUCCESS;
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}
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void edp_aux_ctrl(int enable)
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{
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u32 data;
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data = read32(&edp_auxclk->aux_ctrl);
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if (!enable) {
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data &= ~EDP_AUX_CTRL_ENABLE;
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write32(&edp_auxclk->aux_ctrl, data);
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return;
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}
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data |= EDP_AUX_CTRL_RESET;
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write32(&edp_auxclk->aux_ctrl, data);
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data &= ~EDP_AUX_CTRL_RESET;
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write32(&edp_auxclk->aux_ctrl, data);
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write32(&edp_auxclk->timeout_count, 0xffff);
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write32(&edp_auxclk->aux_limits, 0xffff);
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data |= EDP_AUX_CTRL_ENABLE;
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write32(&edp_auxclk->aux_ctrl, data);
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}
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,327 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <delay.h>
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#include <device/mmio.h>
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#include <edid.h>
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#include <lib.h>
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#include <soc/clock.h>
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#include <soc/display/edp_reg.h>
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#include <soc/display/edp_phy.h>
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#include <string.h>
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#include <timer.h>
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static void edp_phy_ssc_en(bool en)
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{
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if (en) {
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write32(&edp_phy_pll->qserdes_com_ssc_en_center, 0x01);
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write32(&edp_phy_pll->qserdes_com_ssc_adj_per1, 0x00);
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write32(&edp_phy_pll->qserdes_com_ssc_per1, 0x36);
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write32(&edp_phy_pll->qserdes_com_ssc_per2, 0x01);
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write32(&edp_phy_pll->qserdes_com_ssc_step_size1_mode0, 0x5c);
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write32(&edp_phy_pll->qserdes_com_ssc_step_size2_mode0, 0x08);
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} else {
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write32(&edp_phy_pll->qserdes_com_ssc_en_center, 0x00);
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}
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}
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int edp_phy_enable(void)
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{
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write32(&edp_phy->pd_ctl, 0x7D);
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write32(&edp_phy_pll->qserdes_com_bias_en_clkbuflr_en, 0x17);
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write32(&edp_phy->aux_cfg[1], 0x13);
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write32(&edp_phy->aux_cfg[2], 0x24);
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write32(&edp_phy->aux_cfg[3], 0x00);
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write32(&edp_phy->aux_cfg[4], 0x0a);
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write32(&edp_phy->aux_cfg[5], 0x26);
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write32(&edp_phy->aux_cfg[6], 0x0a);
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write32(&edp_phy->aux_cfg[7], 0x03);
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write32(&edp_phy->aux_cfg[8], 0x37);
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write32(&edp_phy->aux_cfg[9], 0x03);
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write32(&edp_phy->aux_interrupt_mask, 0x1f);
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write32(&edp_phy->mode, 0xFC);
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if (!wait_us(1000, read32(&edp_phy_pll->qserdes_com_cmn_status) & BIT(7)))
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printk(BIOS_ERR, "%s: refgen not ready : 0x%x\n", __func__,
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read32(&edp_phy_pll->qserdes_com_cmn_status));
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write32(&edp_phy_lane_tx0->tx_ldo_config, 0x01);
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write32(&edp_phy_lane_tx1->tx_ldo_config, 0x01);
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write32(&edp_phy_lane_tx0->tx_lane_mode1, 0x00);
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write32(&edp_phy_lane_tx1->tx_lane_mode1, 0x00);
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return 0;
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}
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|
||||
static const u8 edp_hbr2_pre_emphasis[4][4] = {
|
||||
{0x0c, 0x15, 0x19, 0x1e}, /* pe0, 0 db */
|
||||
{0x08, 0x15, 0x19, 0xFF}, /* pe1, 3.5 db */
|
||||
{0x0e, 0x14, 0xFF, 0xFF}, /* pe2, 6.0 db */
|
||||
{0x0d, 0xFF, 0xFF, 0xFF} /* pe3, 9.5 db */
|
||||
};
|
||||
|
||||
static const u8 edp_hbr2_voltage_swing[4][4] = {
|
||||
{0xb, 0x11, 0x17, 0x1c}, /* sw0, 0.4v */
|
||||
{0x10, 0x19, 0x1f, 0xFF}, /* sw1, 0.6 v */
|
||||
{0x19, 0x1F, 0xFF, 0xFF}, /* sw1, 0.8 v */
|
||||
{0x1f, 0xFF, 0xFF, 0xFF} /* sw1, 1.2 v, optional */
|
||||
};
|
||||
|
||||
void edp_phy_vm_pe_init(void)
|
||||
{
|
||||
write32(&edp_phy_lane_tx0->tx_drv_lvl, edp_hbr2_voltage_swing[0][0]);
|
||||
write32(&edp_phy_lane_tx0->tx_emp_post1_lvl,
|
||||
edp_hbr2_pre_emphasis[0][0]);
|
||||
write32(&edp_phy_lane_tx1->tx_drv_lvl, edp_hbr2_voltage_swing[0][0]);
|
||||
write32(&edp_phy_lane_tx1->tx_emp_post1_lvl,
|
||||
edp_hbr2_pre_emphasis[0][0]);
|
||||
|
||||
write32(&edp_phy_lane_tx0->tx_highz_drvr_en, 4);
|
||||
write32(&edp_phy_lane_tx0->tx_transceiver_bias_en, 3);
|
||||
write32(&edp_phy_lane_tx1->tx_highz_drvr_en, 7);
|
||||
write32(&edp_phy_lane_tx1->tx_transceiver_bias_en, 0);
|
||||
write32(&edp_phy->cfg1, 3);
|
||||
}
|
||||
|
||||
void edp_phy_config(u8 v_level, u8 p_level)
|
||||
{
|
||||
write32(&edp_phy_lane_tx0->tx_drv_lvl,
|
||||
edp_hbr2_voltage_swing[v_level][p_level]);
|
||||
write32(&edp_phy_lane_tx0->tx_emp_post1_lvl,
|
||||
edp_hbr2_pre_emphasis[v_level][p_level]);
|
||||
write32(&edp_phy_lane_tx1->tx_drv_lvl,
|
||||
edp_hbr2_voltage_swing[v_level][p_level]);
|
||||
write32(&edp_phy_lane_tx1->tx_emp_post1_lvl,
|
||||
edp_hbr2_pre_emphasis[v_level][p_level]);
|
||||
}
|
||||
|
||||
static void edp_phy_pll_vco_init(uint32_t link_rate)
|
||||
{
|
||||
edp_phy_ssc_en(true);
|
||||
write32(&edp_phy_pll->qserdes_com_svs_mode_clk_sel, 0x01);
|
||||
write32(&edp_phy_pll->qserdes_com_sysclk_en_sel, 0x0b);
|
||||
write32(&edp_phy_pll->qserdes_com_sys_clk_ctrl, 0x02);
|
||||
write32(&edp_phy_pll->qserdes_com_clk_enable1, 0x0c);
|
||||
write32(&edp_phy_pll->qserdes_com_sysclk_buf_enable, 0x06);
|
||||
write32(&edp_phy_pll->qserdes_com_clk_sel, 0x30);
|
||||
write32(&edp_phy_pll->qserdes_com_pll_ivco, 0x07);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp_en, 0x04);
|
||||
write32(&edp_phy_pll->qserdes_com_pll_cctrl_mode0, 0x36);
|
||||
write32(&edp_phy_pll->qserdes_com_pll_rctrl_mode0, 0x16);
|
||||
write32(&edp_phy_pll->qserdes_com_cp_ctrl_mode0, 0x06);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start1_mode0, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_cmn_config, 0x02);
|
||||
write32(&edp_phy_pll->qserdes_com_integloop_gain0_mode0, 0x3f);
|
||||
write32(&edp_phy_pll->qserdes_com_integloop_gain1_mode0, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune_map, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_bg_timer, 0x0a);
|
||||
write32(&edp_phy_pll->qserdes_com_coreclk_div_mode0, 0x14);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune_ctrl, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_bias_en_clkbuflr_en, 0x17);
|
||||
write32(&edp_phy_pll->qserdes_com_core_clk_en, 0x0f);
|
||||
|
||||
switch (link_rate) {
|
||||
case 162000:
|
||||
write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x05);
|
||||
write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x69);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x80);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x07);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x6f);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x08);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune1_mode0, 0xa0);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune2_mode0, 0x03);
|
||||
break;
|
||||
case 216000:
|
||||
write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x04);
|
||||
write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x70);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x08);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x3f);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x0b);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune1_mode0, 0x34);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune2_mode0, 0x03);
|
||||
break;
|
||||
case 243000:
|
||||
write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x04);
|
||||
write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x7e);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x09);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0xa7);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x0c);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune1_mode0, 0x5c);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune2_mode0, 0x02);
|
||||
break;
|
||||
case 270000:
|
||||
write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x03);
|
||||
write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x69);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x80);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x07);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x0f);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x0e);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune1_mode0, 0xa0);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune2_mode0, 0x03);
|
||||
break;
|
||||
case 324000:
|
||||
write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x03);
|
||||
write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x7e);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x09);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0xdf);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x10);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune1_mode0, 0x5c);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune2_mode0, 0x02);
|
||||
break;
|
||||
case 432000:
|
||||
write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x01);
|
||||
write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x70);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x08);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x7f);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x16);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune1_mode0, 0x34);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune2_mode0, 0x03);
|
||||
break;
|
||||
case 540000:
|
||||
write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x01);
|
||||
write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x8c);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x0a);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x1f);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x1c);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune1_mode0, 0x84);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune2_mode0, 0x01);
|
||||
break;
|
||||
case 594000:
|
||||
write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x01);
|
||||
write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x9a);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x0b);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0xef);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x1e);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune1_mode0, 0xac);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune2_mode0, 0x00);
|
||||
break;
|
||||
case 810000:
|
||||
write32(&edp_phy_pll->qserdes_com_hsclk_sel, 0x00);
|
||||
write32(&edp_phy_pll->qserdes_com_dec_start_mode0, 0x69);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start2_mode0, 0x80);
|
||||
write32(&edp_phy_pll->qserdes_com_div_frac_start3_mode0, 0x07);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp1_mode0, 0x2f);
|
||||
write32(&edp_phy_pll->qserdes_com_lock_cmp2_mode0, 0x2a);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune1_mode0, 0xa0);
|
||||
write32(&edp_phy_pll->qserdes_com_vco_tune2_mode0, 0x03);
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "%s: Invalid link rate. rate = %u\n", __func__,
|
||||
link_rate);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void edp_phy_lanes_init(void)
|
||||
{
|
||||
write32(&edp_phy_lane_tx0->tx_transceiver_bias_en, 0x03);
|
||||
write32(&edp_phy_lane_tx0->tx_clk_buf_enable, 0x0f);
|
||||
write32(&edp_phy_lane_tx0->tx_reset_tsync_en, 0x03);
|
||||
write32(&edp_phy_lane_tx0->tx_tran_drvr_emp_en, 0x01);
|
||||
write32(&edp_phy_lane_tx0->tx_tx_band, 0x4);
|
||||
|
||||
write32(&edp_phy_lane_tx1->tx_transceiver_bias_en, 0x03);
|
||||
write32(&edp_phy_lane_tx1->tx_clk_buf_enable, 0x0f);
|
||||
write32(&edp_phy_lane_tx1->tx_reset_tsync_en, 0x03);
|
||||
write32(&edp_phy_lane_tx1->tx_tran_drvr_emp_en, 0x01);
|
||||
write32(&edp_phy_lane_tx1->tx_tx_band, 0x4);
|
||||
}
|
||||
|
||||
static void edp_lanes_configure(void)
|
||||
{
|
||||
write32(&edp_phy_lane_tx0->tx_highz_drvr_en, 0x1f);
|
||||
write32(&edp_phy_lane_tx0->tx_highz_drvr_en, 0x04);
|
||||
write32(&edp_phy_lane_tx0->tx_tx_pol_inv, 0x00);
|
||||
|
||||
write32(&edp_phy_lane_tx1->tx_highz_drvr_en, 0x1f);
|
||||
write32(&edp_phy_lane_tx1->tx_highz_drvr_en, 0x04);
|
||||
write32(&edp_phy_lane_tx1->tx_tx_pol_inv, 0x00);
|
||||
|
||||
write32(&edp_phy_lane_tx1->tx_highz_drvr_en, 0x04);
|
||||
write32(&edp_phy_lane_tx1->tx_tx_pol_inv, 0x00);
|
||||
|
||||
write32(&edp_phy_lane_tx0->tx_drv_lvl_offset, 0x10);
|
||||
write32(&edp_phy_lane_tx1->tx_drv_lvl_offset, 0x10);
|
||||
|
||||
write32(&edp_phy_lane_tx0->tx_rescode_lane_offset_tx0, 0x11);
|
||||
write32(&edp_phy_lane_tx0->tx_rescode_lane_offset_tx1, 0x11);
|
||||
|
||||
write32(&edp_phy_lane_tx1->tx_rescode_lane_offset_tx0, 0x11);
|
||||
write32(&edp_phy_lane_tx1->tx_rescode_lane_offset_tx1, 0x11);
|
||||
}
|
||||
|
||||
static int edp_phy_pll_vco_configure(uint32_t link_rate)
|
||||
{
|
||||
u32 phy_vco_div = 0;
|
||||
|
||||
switch (link_rate) {
|
||||
case 162000:
|
||||
phy_vco_div = 2;
|
||||
break;
|
||||
case 216000:
|
||||
case 243000:
|
||||
case 270000:
|
||||
phy_vco_div = 1;
|
||||
break;
|
||||
case 324000:
|
||||
case 432000:
|
||||
case 540000:
|
||||
phy_vco_div = 2;
|
||||
break;
|
||||
case 594000:
|
||||
case 810000:
|
||||
phy_vco_div = 0;
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_ERR, "%s: Invalid link rate. rate = %u\n", __func__,
|
||||
link_rate);
|
||||
break;
|
||||
}
|
||||
|
||||
write32(&edp_phy->vco_div, phy_vco_div);
|
||||
write32(&edp_phy->cfg, 0x01);
|
||||
write32(&edp_phy->cfg, 0x05);
|
||||
write32(&edp_phy->cfg, 0x01);
|
||||
write32(&edp_phy->cfg, 0x09);
|
||||
write32(&edp_phy_pll->qserdes_com_resetsm_cntrl, 0x20);
|
||||
if (!wait_us(10000, read32(&edp_phy_pll->qserdes_com_c_ready_status) & BIT(0))) {
|
||||
printk(BIOS_ERR, "%s: PLL not locked. Status\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
write32(&edp_phy->cfg, 0x19);
|
||||
edp_lanes_configure();
|
||||
edp_phy_vm_pe_init();
|
||||
if (!wait_us(10000, read32(&edp_phy->status) & BIT(1))) {
|
||||
printk(BIOS_ERR, "%s: PHY not ready. Status\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
write32(&edp_phy->cfg, 0x18);
|
||||
write32(&edp_phy->cfg, 0x19);
|
||||
if (!wait_us(10000, read32(&edp_phy_pll->qserdes_com_c_ready_status) & BIT(0))) {
|
||||
printk(BIOS_ERR, "%s: PLL not locked. Status\n", __func__);
|
||||
return -1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int edp_phy_power_on(uint32_t link_rate)
|
||||
{
|
||||
int ret = 0;
|
||||
edp_phy_pll_vco_init(link_rate);
|
||||
|
||||
write32(&edp_phy->tx0_tx1_lane_ctl, 0x5);
|
||||
write32(&edp_phy->tx2_tx3_lane_ctl, 0x5);
|
||||
edp_phy_lanes_init();
|
||||
ret = edp_phy_pll_vco_configure(link_rate);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _EDP_AUX_H
|
||||
#define _EDP_AUX_H
|
||||
|
||||
#include <types.h>
|
||||
|
||||
#define DP_AUX_I2C_WRITE 0x0
|
||||
#define DP_AUX_I2C_READ 0x1
|
||||
#define DP_AUX_I2C_STATUS 0x2
|
||||
#define DP_AUX_I2C_MOT 0x4
|
||||
#define DP_AUX_NATIVE_WRITE 0x8
|
||||
#define DP_AUX_NATIVE_READ 0x9
|
||||
#define REG_EDP_AUX_CTRL (0x00000030)
|
||||
#define EDP_AUX_CTRL_ENABLE (0x00000001)
|
||||
#define EDP_AUX_CTRL_RESET (0x00000002)
|
||||
|
||||
#define REG_EDP_AUX_DATA (0x00000034)
|
||||
#define EDP_AUX_DATA_READ (0x00000001)
|
||||
#define EDP_AUX_DATA_DATA__MASK (0x0000ff00)
|
||||
#define EDP_AUX_DATA_DATA__SHIFT (8)
|
||||
|
||||
#define EDP_AUX_DATA_INDEX__MASK (0x00ff0000)
|
||||
#define EDP_AUX_DATA_INDEX__SHIFT (16)
|
||||
|
||||
#define EDP_AUX_DATA_INDEX_WRITE (0x80000000)
|
||||
|
||||
#define REG_EDP_AUX_TRANS_CTRL (0x00000038)
|
||||
#define EDP_AUX_TRANS_CTRL_I2C (0x00000100)
|
||||
#define EDP_AUX_TRANS_CTRL_GO (0x00000200)
|
||||
#define EDP_AUX_TRANS_CTRL_NO_SEND_ADDR (0x00000400)
|
||||
#define EDP_AUX_TRANS_CTRL_NO_SEND_STOP (0x00000800)
|
||||
|
||||
#define REG_EDP_TIMEOUT_COUNT (0x0000003C)
|
||||
#define REG_EDP_AUX_LIMITS (0x00000040)
|
||||
#define REG_EDP_AUX_STATUS (0x00000044)
|
||||
#define AUX_CMD_READ (BIT(4))
|
||||
|
||||
enum {
|
||||
EDID_LENGTH = 128,
|
||||
EDID_I2C_ADDR = 0x50,
|
||||
EDID_EXTENSION_FLAG = 0x7e,
|
||||
};
|
||||
|
||||
static inline uint32_t EDP_AUX_DATA_DATA(uint32_t val)
|
||||
{
|
||||
return ((val) << EDP_AUX_DATA_DATA__SHIFT) & EDP_AUX_DATA_DATA__MASK;
|
||||
}
|
||||
|
||||
static inline uint32_t EDP_AUX_DATA_INDEX(uint32_t val)
|
||||
{
|
||||
return ((val) << EDP_AUX_DATA_INDEX__SHIFT) & EDP_AUX_DATA_INDEX__MASK;
|
||||
}
|
||||
|
||||
void edp_aux_ctrl(int enable);
|
||||
int edp_read_edid(struct edid *out);
|
||||
ssize_t edp_aux_transfer(unsigned int address, u8 request, void *buffer, size_t size);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _EDP_CTRL_H
|
||||
#define _EDP_CTRL_H
|
||||
|
||||
#include <types.h>
|
||||
#include <stdint.h>
|
||||
|
||||
enum cb_err edp_ctrl_init(struct edid *edid);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _EDP_PHY_H
|
||||
#define _EDP_PHY_H
|
||||
|
||||
#include <types.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void edp_phy_config(u8 v_level, u8 p_level);
|
||||
void edp_phy_vm_pe_init(void);
|
||||
int edp_phy_enable(void);
|
||||
int edp_phy_power_on(uint32_t link_rate);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,328 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _EDP_REG_H_
|
||||
#define _EDP_REG_H_
|
||||
|
||||
#include <types.h>
|
||||
#include <stdint.h>
|
||||
|
||||
struct edp_ahbclk_regs {
|
||||
uint32_t hw_version;
|
||||
uint32_t reserved0[3];
|
||||
uint32_t sw_reset;
|
||||
uint32_t phy_ctrl;
|
||||
uint32_t clk_ctrl;
|
||||
uint32_t clk_active;
|
||||
uint32_t interrupt_status;
|
||||
uint32_t interrupt_status2;
|
||||
uint32_t interrupt_status3;
|
||||
};
|
||||
|
||||
check_member(edp_ahbclk_regs, sw_reset, 0x10);
|
||||
|
||||
struct edp_auxclk_regs {
|
||||
uint32_t hpd_ctrl;
|
||||
uint32_t hpd_int_status;
|
||||
uint32_t hpd_int_ack;
|
||||
uint32_t hpd_int_mask;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t hpd_reftimer;
|
||||
uint32_t hpd_event_time0;
|
||||
uint32_t hpd_event_time1;
|
||||
uint32_t reserved1[3];
|
||||
uint32_t aux_ctrl;
|
||||
uint32_t aux_data;
|
||||
uint32_t aux_trans_ctrl;
|
||||
uint32_t timeout_count;
|
||||
uint32_t aux_limits;
|
||||
uint32_t status;
|
||||
uint32_t reserved2[22];
|
||||
uint32_t interrupt_trans_num;
|
||||
};
|
||||
check_member(edp_auxclk_regs, hpd_reftimer, 0x18);
|
||||
check_member(edp_auxclk_regs, aux_ctrl, 0x30);
|
||||
check_member(edp_auxclk_regs, interrupt_trans_num, 0xa0);
|
||||
|
||||
struct edp_lclk_regs {
|
||||
uint32_t mainlink_ctrl;
|
||||
uint32_t state_ctrl;
|
||||
uint32_t configuration_ctrl;
|
||||
uint32_t top_bot_interlaced_num_of_lanes;
|
||||
uint32_t software_mvid;
|
||||
uint32_t reserved0;
|
||||
uint32_t software_nvid;
|
||||
uint32_t total_hor_ver;
|
||||
uint32_t start_hor_ver_from_sync;
|
||||
uint32_t hysnc_vsync_width_polarity;
|
||||
uint32_t active_hor_ver;
|
||||
uint32_t misc1_misc0;
|
||||
uint32_t valid_boundary;
|
||||
uint32_t valid_boundary2;
|
||||
uint32_t logcial2physical_lane_mapping;
|
||||
uint32_t reserved1;
|
||||
uint32_t mainlink_ready;
|
||||
uint32_t mainlink_levels;
|
||||
uint32_t mainlink_levels2;
|
||||
uint32_t tu;
|
||||
};
|
||||
|
||||
struct edp_p0clk_regs {
|
||||
uint32_t bist_enable;
|
||||
uint32_t reserved0[3];
|
||||
uint32_t timing_engine_en;
|
||||
uint32_t intf_config;
|
||||
uint32_t hsync_ctl;
|
||||
uint32_t vsync_period_f0;
|
||||
uint32_t vsync_period_f1;
|
||||
uint32_t vsync_pulse_width_f0;
|
||||
uint32_t vsync_pulse_width_f1;
|
||||
uint32_t display_v_start_f0;
|
||||
uint32_t display_v_start_f1;
|
||||
uint32_t display_v_end_f0;
|
||||
uint32_t display_v_end_f1;
|
||||
uint32_t active_v_start_f0;
|
||||
uint32_t active_v_start_f1;
|
||||
uint32_t active_v_end_f0;
|
||||
uint32_t active_v_end_f1;
|
||||
uint32_t display_hctl;
|
||||
uint32_t active_hctl;
|
||||
uint32_t hsync_skew;
|
||||
uint32_t polarity_ctl;
|
||||
uint32_t reserved1;
|
||||
uint32_t tpg_main_control;
|
||||
uint32_t tpg_video_config;
|
||||
uint32_t tpg_component_limits;
|
||||
uint32_t tpg_rectangle;
|
||||
uint32_t tpg_initial_value;
|
||||
uint32_t tpg_color_changing_frames;
|
||||
uint32_t tpg_rgb_mapping;
|
||||
uint32_t dsc_dto;
|
||||
};
|
||||
|
||||
check_member(edp_p0clk_regs, dsc_dto, 0x7c);
|
||||
|
||||
struct edp_phy_regs {
|
||||
uint32_t revision_id0;
|
||||
uint32_t revision_id1;
|
||||
uint32_t revision_id2;
|
||||
uint32_t revision_id3;
|
||||
uint32_t cfg;
|
||||
uint32_t cfg1;
|
||||
uint32_t cfg2;
|
||||
uint32_t pd_ctl;
|
||||
uint32_t mode;
|
||||
uint32_t aux_cfg[13];
|
||||
uint32_t aux_interrupt_mask;
|
||||
uint32_t aux_interrupt_clr;
|
||||
uint32_t aux_bist_cfg;
|
||||
uint32_t aux_bist_prbs_seed;
|
||||
uint32_t aux_bist_prbs_poly;
|
||||
uint32_t aux_tx_prog_pat_16b_lsb;
|
||||
uint32_t aux_tx_prog_pat_16b_msb;
|
||||
uint32_t vco_div;
|
||||
uint32_t tsync_ovrd;
|
||||
uint32_t tx0_tx1_lane_ctl;
|
||||
uint32_t tx0_tx1_bist_cfg[4];
|
||||
uint32_t tx0_tx1_prbs_seed_byte0;
|
||||
uint32_t tx0_tx1_prbs_seed_byte1;
|
||||
uint32_t tx0_tx1_bist_pattern0;
|
||||
uint32_t tx0_tx1_bist_pattern1;
|
||||
uint32_t tx2_tx3_lane_ctl;
|
||||
uint32_t tx2_tx3_bist_cfg[4];
|
||||
uint32_t tx2_tx3_prbs_seed_byte0;
|
||||
uint32_t tx2_tx3_prbs_seed_byte1;
|
||||
uint32_t tx2_tx3_bist_pattern0;
|
||||
uint32_t tx2_tx3_bist_pattern1;
|
||||
uint32_t misr_ctl;
|
||||
uint32_t debug_bus_sel;
|
||||
uint32_t spare[4];
|
||||
uint32_t aux_interrupt_status;
|
||||
uint32_t status;
|
||||
};
|
||||
|
||||
struct edp_phy_lane_regs {
|
||||
uint32_t tx_clk_buf_enable;
|
||||
uint32_t tx_emp_post1_lvl;
|
||||
uint32_t tx_post2_emph;
|
||||
uint32_t tx_boost_lvl_up_dn;
|
||||
uint32_t tx_idle_lvl_large_amp;
|
||||
uint32_t tx_drv_lvl;
|
||||
uint32_t tx_drv_lvl_offset;
|
||||
uint32_t tx_reset_tsync_en;
|
||||
uint32_t tx_pre_emph;
|
||||
uint32_t tx_interface_select;
|
||||
uint32_t tx_tx_band;
|
||||
uint32_t tx_slew_cntl;
|
||||
uint32_t tx_lpb0_cfg[3];
|
||||
uint32_t tx_rescode_lane_tx;
|
||||
uint32_t tx_rescode_lane_tx1;
|
||||
uint32_t tx_rescode_lane_offset_tx0;
|
||||
uint32_t tx_rescode_lane_offset_tx1;
|
||||
uint32_t tx_serdes_byp_en_out;
|
||||
uint32_t tx_dbg_bus_sel;
|
||||
uint32_t tx_transceiver_bias_en;
|
||||
uint32_t tx_highz_drvr_en;
|
||||
uint32_t tx_tx_pol_inv;
|
||||
uint32_t tx_parrate_rec_detect_idle_en;
|
||||
uint32_t tx_lane_mode1;
|
||||
uint32_t tx_lane_mode2;
|
||||
uint32_t tx_atb_sel1;
|
||||
uint32_t tx_atb_sel2;
|
||||
uint32_t tx_reset_gen_muxes;
|
||||
uint32_t tx_tran_drvr_emp_en;
|
||||
uint32_t tx_vmode_ctrl1;
|
||||
uint32_t tx_lane_dig_config;
|
||||
uint32_t tx_ldo_config;
|
||||
uint32_t tx_dig_bkup_ctrl;
|
||||
};
|
||||
|
||||
struct edp_phy_pll_regs {
|
||||
uint32_t qserdes_com_atb_sel1;
|
||||
uint32_t qserdes_com_atb_sel2;
|
||||
uint32_t qserdes_com_freq_update;
|
||||
uint32_t qserdes_com_bg_timer;
|
||||
uint32_t qserdes_com_ssc_en_center;
|
||||
uint32_t qserdes_com_ssc_adj_per1;
|
||||
uint32_t qserdes_com_ssc_adj_per2;
|
||||
uint32_t qserdes_com_ssc_per1;
|
||||
uint32_t qserdes_com_ssc_per2;
|
||||
uint32_t qserdes_com_ssc_step_size1_mode0;
|
||||
uint32_t qserdes_com_ssc_step_size2_mode0;
|
||||
uint32_t qserdes_com_ssc_step_size3_mode0;
|
||||
uint32_t qserdes_com_ssc_step_size1_mode1;
|
||||
uint32_t qserdes_com_ssc_step_size2_mode1;
|
||||
uint32_t qserdes_com_ssc_step_size3_mode1;
|
||||
uint32_t qserdes_com_post_div;
|
||||
uint32_t qserdes_com_post_div_mux;
|
||||
uint32_t qserdes_com_bias_en_clkbuflr_en;
|
||||
uint32_t qserdes_com_clk_enable1;
|
||||
uint32_t qserdes_com_sys_clk_ctrl;
|
||||
uint32_t qserdes_com_sysclk_buf_enable;
|
||||
uint32_t qserdes_com_pll_en;
|
||||
uint32_t qserdes_com_pll_ivco;
|
||||
uint32_t qserdes_com_cmn_iterim;
|
||||
uint32_t qserdes_com_cmn_iptrim;
|
||||
uint32_t qserdes_com_ep_clk_detect_ctrl;
|
||||
uint32_t qserdes_com_sysclk_det_comp_status;
|
||||
uint32_t qserdes_com_clk_ep_div_mode0;
|
||||
uint32_t qserdes_com_clk_ep_div_mode1;
|
||||
uint32_t qserdes_com_cp_ctrl_mode0;
|
||||
uint32_t qserdes_com_cp_ctrl_mode1;
|
||||
uint32_t qserdes_com_pll_rctrl_mode0;
|
||||
uint32_t qserdes_com_pll_rctrl_mode1;
|
||||
uint32_t qserdes_com_pll_cctrl_mode0;
|
||||
uint32_t qserdes_com_pll_cctrl_mode1;
|
||||
uint32_t qserdes_com_pll_cntrl;
|
||||
uint32_t qserdes_com_bias_en_ctrl_by_psm;
|
||||
uint32_t qserdes_com_sysclk_en_sel;
|
||||
uint32_t qserdes_com_cml_sysclk_sel;
|
||||
uint32_t qserdes_com_resetsm_cntrl;
|
||||
uint32_t qserdes_com_resetsm_cntrl2;
|
||||
uint32_t qserdes_com_lock_cmp_en;
|
||||
uint32_t qserdes_com_lock_cmp_cfg;
|
||||
uint32_t qserdes_com_lock_cmp1_mode0;
|
||||
uint32_t qserdes_com_lock_cmp2_mode0;
|
||||
uint32_t qserdes_com_lock_cmp1_mode1;
|
||||
uint32_t qserdes_com_lock_cmp2_mode1;
|
||||
uint32_t qserdes_com_dec_start_mode0;
|
||||
uint32_t qserdes_com_dec_start_msb_mode0;
|
||||
uint32_t qserdes_com_dec_start_mode1;
|
||||
uint32_t qserdes_com_dec_start_msb_mode1;
|
||||
uint32_t qserdes_com_div_frac_start1_mode0;
|
||||
uint32_t qserdes_com_div_frac_start2_mode0;
|
||||
uint32_t qserdes_com_div_frac_start3_mode0;
|
||||
uint32_t qserdes_com_div_frac_start1_mode1;
|
||||
uint32_t qserdes_com_div_frac_start2_mode1;
|
||||
uint32_t qserdes_com_div_frac_start3_mode1;
|
||||
uint32_t qserdes_com_integloop_initval;
|
||||
uint32_t qserdes_com_integloop_en;
|
||||
uint32_t qserdes_com_integloop_gain0_mode0;
|
||||
uint32_t qserdes_com_integloop_gain1_mode0;
|
||||
uint32_t qserdes_com_integloop_gain0_mode1;
|
||||
uint32_t qserdes_com_integloop_gain1_mode1;
|
||||
uint32_t qserdes_com_integloop_p_path_gain0;
|
||||
uint32_t qserdes_com_integloop_p_path_gain1;
|
||||
uint32_t qserdes_com_vcoval_deadman_ctrl;
|
||||
uint32_t qserdes_com_vco_tune_ctrl;
|
||||
uint32_t qserdes_com_vco_tune_map;
|
||||
uint32_t qserdes_com_vco_tune1_mode0;
|
||||
uint32_t qserdes_com_vco_tune2_mode0;
|
||||
uint32_t qserdes_com_vco_tune1_mode1;
|
||||
uint32_t qserdes_com_vco_tune2_mode1;
|
||||
uint32_t qserdes_com_vco_tune_initval1;
|
||||
uint32_t qserdes_com_vco_tune_initval2;
|
||||
uint32_t qserdes_com_vco_tune_minval1;
|
||||
uint32_t qserdes_com_vco_tune_minval2;
|
||||
uint32_t qserdes_com_vco_tune_maxval1;
|
||||
uint32_t qserdes_com_vco_tune_maxval2;
|
||||
uint32_t qserdes_com_vco_tune_timer1;
|
||||
uint32_t qserdes_com_vco_tune_timer2;
|
||||
uint32_t qserdes_com_cmn_status;
|
||||
uint32_t qserdes_com_reset_sm_status;
|
||||
uint32_t qserdes_com_restrim_code_status;
|
||||
uint32_t qserdes_com_pllcal_code1_status;
|
||||
uint32_t qserdes_com_pllcal_code2_status;
|
||||
uint32_t qserdes_com_clk_sel;
|
||||
uint32_t qserdes_com_hsclk_sel;
|
||||
uint32_t qserdes_com_hsclk_hs_switch_sel;
|
||||
uint32_t qserdes_com_integloop_bincode_status;
|
||||
uint32_t qserdes_com_pll_analog;
|
||||
uint32_t qserdes_com_coreclk_div_mode0;
|
||||
uint32_t qserdes_com_coreclk_div_mode1;
|
||||
uint32_t qserdes_com_sw_reset;
|
||||
uint32_t qserdes_com_core_clk_en;
|
||||
uint32_t qserdes_com_c_ready_status;
|
||||
uint32_t qserdes_com_cmn_config;
|
||||
uint32_t qserdes_com_cmn_rate_override;
|
||||
uint32_t qserdes_com_svs_mode_clk_sel;
|
||||
};
|
||||
|
||||
/* EDP_STATE_CTRL */
|
||||
enum {
|
||||
SW_LINK_TRAINING_PATTERN1 = BIT(0),
|
||||
SW_LINK_TRAINING_PATTERN2 = BIT(1),
|
||||
SW_LINK_TRAINING_PATTERN3 = BIT(2),
|
||||
SW_LINK_TRAINING_PATTERN4 = BIT(3),
|
||||
SW_LINK_SYMBOL_ERROR_RATE_MEASUREMENT = BIT(4),
|
||||
SW_LINK_PRBS7 = BIT(5),
|
||||
SW_LINK_TEST_CUSTOM_80BIT_PATTERN = BIT(6),
|
||||
SW_SEND_VIDEO = BIT(7),
|
||||
SW_PUSH_IDLE = BIT(8),
|
||||
};
|
||||
|
||||
/* EDP_PHY_AUX_INTERRUPT_CLEAR */
|
||||
enum {
|
||||
RX_STOP_ERR = BIT(0),
|
||||
RX_DEC_ERR = BIT(1),
|
||||
RX_SYNC_ERR = BIT(2),
|
||||
RX_ALIGN_ERR = BIT(3),
|
||||
TX_REQ_ERR = BIT(4),
|
||||
GLOBE_REQ_CLR = BIT(5),
|
||||
};
|
||||
|
||||
enum {
|
||||
EDP_CTRL_BASE = 0xAEA0000,
|
||||
DP_EDP_PHY_BASE = 0xAEC0000,
|
||||
};
|
||||
|
||||
enum {
|
||||
EDP_AHBCLK_BASE = EDP_CTRL_BASE,
|
||||
EDP_AUXCLK_BASE = EDP_CTRL_BASE + 0x200,
|
||||
EDP_LCLK_BASE = EDP_CTRL_BASE + 0x400,
|
||||
EDP_P0CLK_BASE = EDP_CTRL_BASE + 0x1000,
|
||||
EDP_PHY_BASE = DP_EDP_PHY_BASE + 0x2A00,
|
||||
EDP_PHY_LANE_TX0_BASE = DP_EDP_PHY_BASE + 0x2200,
|
||||
EDP_PHY_LANE_TX1_BASE = DP_EDP_PHY_BASE + 0x2600,
|
||||
EDP_PHY_PLL_BASE = DP_EDP_PHY_BASE + 0x2000,
|
||||
};
|
||||
|
||||
static struct edp_ahbclk_regs *const edp_ahbclk = (void *)EDP_AHBCLK_BASE;
|
||||
static struct edp_auxclk_regs *const edp_auxclk = (void *)EDP_AUXCLK_BASE;
|
||||
static struct edp_lclk_regs *const edp_lclk = (void *)EDP_LCLK_BASE;
|
||||
static struct edp_p0clk_regs *const edp_p0clk = (void *)EDP_P0CLK_BASE;
|
||||
static struct edp_phy_regs *const edp_phy = (void *)EDP_PHY_BASE;
|
||||
static struct edp_phy_lane_regs *const edp_phy_lane_tx0 = (void *)EDP_PHY_LANE_TX0_BASE;
|
||||
static struct edp_phy_lane_regs *const edp_phy_lane_tx1 = (void *)EDP_PHY_LANE_TX1_BASE;
|
||||
static struct edp_phy_pll_regs *const edp_phy_pll = (void *)EDP_PHY_PLL_BASE;
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,529 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef _SOC_DISPLAY_MDSS_REG_H_
|
||||
#define _SOC_DISPLAY_MDSS_REG_H_
|
||||
|
||||
#include <types.h>
|
||||
#include <stdint.h>
|
||||
#include <edid.h>
|
||||
|
||||
#define INTF_FLUSH INTF_FLUSH_5
|
||||
|
||||
struct dsi_regs {
|
||||
uint32_t hw_version;
|
||||
uint32_t ctrl;
|
||||
uint32_t reserved0[2];
|
||||
uint32_t video_mode_ctrl;
|
||||
uint32_t reserved1[4];
|
||||
uint32_t video_mode_active_h;
|
||||
uint32_t video_mode_active_v;
|
||||
uint32_t video_mode_active_total;
|
||||
uint32_t video_mode_active_hsync;
|
||||
uint32_t video_mode_active_vsync;
|
||||
uint32_t video_mode_active_vsync_vpos;
|
||||
uint32_t cmd_mode_dma_ctrl;
|
||||
uint32_t cmd_mode_mdp_ctrl;
|
||||
uint32_t cmd_mode_mdp_dcs_cmd_ctrl;
|
||||
uint32_t dma_cmd_offset;
|
||||
uint32_t dma_cmd_length;
|
||||
uint32_t reserved2[2];
|
||||
uint32_t cmd_mode_mdp_stream0_ctrl;
|
||||
uint32_t cmd_mode_mdp_stream0_total;
|
||||
uint32_t cmd_mode_mdp_stream1_ctrl;
|
||||
uint32_t cmd_mode_mdp_stream1_total;
|
||||
uint32_t reserved4[7];
|
||||
uint32_t trig_ctrl;
|
||||
uint32_t reserved5[2];
|
||||
uint32_t cmd_mode_dma_sw_trigger;
|
||||
uint32_t reserved6[3];
|
||||
uint32_t misr_cmd_ctrl;
|
||||
uint32_t misr_video_ctrl;
|
||||
uint32_t lane_status;
|
||||
uint32_t lane_ctrl;
|
||||
uint32_t reserved7[3];
|
||||
uint32_t hs_timer_ctrl;
|
||||
uint32_t timeout_status;
|
||||
uint32_t clkout_timing_ctrl;
|
||||
uint32_t eot_packet;
|
||||
uint32_t eot_packet_ctrl;
|
||||
uint32_t reserved8[15];
|
||||
uint32_t err_int_mask0;
|
||||
uint32_t int_ctrl;
|
||||
uint32_t iobist_ctrl;
|
||||
uint32_t soft_reset;
|
||||
uint32_t clk_ctrl;
|
||||
uint32_t reserved9[15];
|
||||
uint32_t test_pattern_gen_ctrl;
|
||||
uint32_t reserved10[7];
|
||||
uint32_t test_pattern_gen_cmd_dma_init_val;
|
||||
uint32_t reserved11[14];
|
||||
uint32_t cmd_mode_mdp_ctrl2;
|
||||
uint32_t reserved12[12];
|
||||
uint32_t tpg_dma_fifo_reset;
|
||||
uint32_t reserved13[44];
|
||||
uint32_t video_compression_mode_ctrl;
|
||||
uint32_t video_compression_mode_ctrl2;
|
||||
uint32_t cmd_compression_mode_ctrl;
|
||||
uint32_t cmd_compression_mode_ctrl2;
|
||||
uint32_t cmd_compression_mode_ctrl3;
|
||||
};
|
||||
|
||||
check_member(dsi_regs, video_mode_active_h, 0x24);
|
||||
check_member(dsi_regs, cmd_mode_mdp_stream0_ctrl, 0x58);
|
||||
check_member(dsi_regs, trig_ctrl, 0x84);
|
||||
check_member(dsi_regs, cmd_mode_dma_sw_trigger, 0x90);
|
||||
check_member(dsi_regs, misr_cmd_ctrl, 0xA0);
|
||||
check_member(dsi_regs, hs_timer_ctrl, 0xBC);
|
||||
check_member(dsi_regs, err_int_mask0, 0x10C);
|
||||
check_member(dsi_regs, test_pattern_gen_ctrl, 0x15c);
|
||||
check_member(dsi_regs, test_pattern_gen_cmd_dma_init_val, 0x17c);
|
||||
check_member(dsi_regs, cmd_mode_mdp_ctrl2, 0x1B8);
|
||||
check_member(dsi_regs, tpg_dma_fifo_reset, 0x1EC);
|
||||
check_member(dsi_regs, video_compression_mode_ctrl, 0x2A0);
|
||||
|
||||
struct dsi_phy_regs {
|
||||
uint32_t phy_cmn_revision_id0;
|
||||
uint32_t reserved0[3];
|
||||
uint32_t phy_cmn_clk_cfg0;
|
||||
uint32_t phy_cmn_clk_cfg1;
|
||||
uint32_t phy_cmn_glbl_ctrl;
|
||||
uint32_t phy_cmn_rbuf_ctrl;
|
||||
uint32_t phy_cmn_vreg_ctrl;
|
||||
uint32_t phy_cmn_ctrl0;
|
||||
uint32_t phy_cmn_ctrl1;
|
||||
uint32_t phy_cmn_ctrl2;
|
||||
uint32_t phy_cmn_lane_cfg0;
|
||||
uint32_t phy_cmn_lane_cfg1;
|
||||
uint32_t phy_cmn_pll_ctrl;
|
||||
uint32_t reserved1[23];
|
||||
uint32_t phy_cmn_dsi_lane_ctrl0;
|
||||
uint32_t reserved2[4];
|
||||
uint32_t phy_cmn_timing_ctrl[12];
|
||||
uint32_t reserved3[4];
|
||||
uint32_t phy_cmn_phy_status;
|
||||
uint32_t reserved4[68];
|
||||
struct {
|
||||
uint32_t dln0_cfg[4];
|
||||
uint32_t dln0_test_datapath;
|
||||
uint32_t dln0_pin_swap;
|
||||
uint32_t dln0_hstx_str_ctrl;
|
||||
uint32_t dln0_offset_top_ctrl;
|
||||
uint32_t dln0_offset_bot_ctrl;
|
||||
uint32_t dln0_lptx_str_ctrl;
|
||||
uint32_t dln0_lprx_ctrl;
|
||||
uint32_t dln0_tx_dctrl;
|
||||
uint32_t reserved5[20];
|
||||
} phy_ln_regs[5];
|
||||
};
|
||||
|
||||
check_member(dsi_phy_regs, phy_cmn_clk_cfg0, 0x10);
|
||||
check_member(dsi_phy_regs, phy_cmn_dsi_lane_ctrl0, 0x98);
|
||||
check_member(dsi_phy_regs, phy_cmn_timing_ctrl[0], 0xAC);
|
||||
check_member(dsi_phy_regs, phy_cmn_phy_status, 0xEC);
|
||||
check_member(dsi_phy_regs, phy_ln_regs[0], 0x200);
|
||||
check_member(dsi_phy_regs, phy_ln_regs[1], 0x280);
|
||||
check_member(dsi_phy_regs, phy_ln_regs[2], 0x300);
|
||||
check_member(dsi_phy_regs, phy_ln_regs[3], 0x380);
|
||||
check_member(dsi_phy_regs, phy_ln_regs[4], 0x400);
|
||||
|
||||
struct dsi_phy_pll_qlink_regs {
|
||||
uint32_t pll_analog_ctrls_one;
|
||||
uint32_t pll_analog_ctrls_two;
|
||||
uint32_t pll_int_loop_settings;
|
||||
uint32_t pll_int_loop_settings_two;
|
||||
uint32_t pll_analog_ctrls_three;
|
||||
uint32_t pll_analog_ctrls_four;
|
||||
uint32_t pll_int_loop_ctrls;
|
||||
uint32_t pll_dsm_divider;
|
||||
uint32_t pll_feedback_divider;
|
||||
uint32_t pll_system_muxes;
|
||||
uint32_t pll_freq_update_ctrl_overrides;
|
||||
uint32_t pll_cmode;
|
||||
uint32_t pll_cal_settings;
|
||||
uint32_t pll_band_sel_cal_timer_low;
|
||||
uint32_t pll_band_sel_cal_timer_high;
|
||||
uint32_t pll_band_sel_cal_settings;
|
||||
uint32_t pll_band_sel_min;
|
||||
uint32_t pll_band_sel_max;
|
||||
uint32_t pll_band_sel_pfilt;
|
||||
uint32_t pll_band_sel_ifilt;
|
||||
uint32_t pll_band_sel_cal_settings_two;
|
||||
uint32_t pll_band_sel_cal_settings_three;
|
||||
uint32_t pll_band_sel_cal_settings_four;
|
||||
uint32_t pll_band_sel_icode_high;
|
||||
uint32_t pll_band_sel_icode_low;
|
||||
uint32_t pll_freq_detect_settings_one;
|
||||
uint32_t pll_freq_detect_thresh;
|
||||
uint32_t pll_freq_det_refclk_high;
|
||||
uint32_t pll_freq_det_refclk_low;
|
||||
uint32_t pll_freq_det_pllclk_high;
|
||||
uint32_t pll_freq_det_pllclk_low;
|
||||
uint32_t pll_pfilt;
|
||||
uint32_t pll_ifilt;
|
||||
uint32_t pll_pll_gain;
|
||||
uint32_t pll_icode_low;
|
||||
uint32_t pll_icode_high;
|
||||
uint32_t pll_lockdet;
|
||||
uint32_t pll_outdiv;
|
||||
uint32_t pll_fastlock_ctrl;
|
||||
uint32_t pll_pass_out_override_one;
|
||||
uint32_t pll_pass_out_override_two;
|
||||
uint32_t pll_core_override;
|
||||
uint32_t pll_core_input_override;
|
||||
uint32_t pll_rate_change;
|
||||
uint32_t pll_digital_timers;
|
||||
uint32_t pll_digital_timers_two;
|
||||
uint32_t pll_decimal_div_start;
|
||||
uint32_t pll_frac_div_start_low;
|
||||
uint32_t pll_frac_div_start_mid;
|
||||
uint32_t pll_frac_div_start_high;
|
||||
uint32_t pll_dec_frac_muxes;
|
||||
uint32_t pll_decimal_div_start_1;
|
||||
uint32_t pll_frac_div_start_low1;
|
||||
uint32_t pll_frac_div_start_mid1;
|
||||
uint32_t pll_frac_div_start_high1;
|
||||
uint32_t reserve0[4];
|
||||
uint32_t pll_mash_ctrl;
|
||||
uint32_t reserved1[6];
|
||||
uint32_t pll_ssc_mux_ctrl;
|
||||
uint32_t pll_ssc_stepsize_low1;
|
||||
uint32_t pll_ssc_stepsize_high1;
|
||||
uint32_t pll_ssc_div_per_low_1;
|
||||
uint32_t pll_ssc_div_per_high_1;
|
||||
uint32_t pll_ssc_adjper_low_1;
|
||||
uint32_t pll_ssc_adjper_high_1;
|
||||
uint32_t reserved2[6];
|
||||
uint32_t pll_ssc_ctrl;
|
||||
uint32_t pll_outdiv_rate;
|
||||
uint32_t pll_lockdet_rate[2];
|
||||
uint32_t pll_prop_gain_rate[2];
|
||||
uint32_t pll_band_set_rate[2];
|
||||
uint32_t pll_gain_ifilt_band[2];
|
||||
uint32_t pll_fl_int_gain_pfilt_band[2];
|
||||
uint32_t pll_pll_fastlock_en_band;
|
||||
uint32_t reserved9[3];
|
||||
uint32_t pll_freq_tune_accum_init_mux;
|
||||
uint32_t pll_lock_override;
|
||||
uint32_t pll_lock_delay;
|
||||
uint32_t pll_lock_min_delay;
|
||||
uint32_t pll_clock_inverters;
|
||||
uint32_t pll_spare_and_jpc_overrides;
|
||||
uint32_t pll_bias_ctrl_1;
|
||||
uint32_t pll_bias_ctrl_2;
|
||||
uint32_t pll_alog_obsv_bus_ctrl_1;
|
||||
uint32_t pll_common_status_one;
|
||||
};
|
||||
check_member(dsi_phy_pll_qlink_regs, pll_mash_ctrl, 0xEC);
|
||||
check_member(dsi_phy_pll_qlink_regs, pll_ssc_mux_ctrl, 0x108);
|
||||
check_member(dsi_phy_pll_qlink_regs, pll_ssc_ctrl, 0x13C);
|
||||
check_member(dsi_phy_pll_qlink_regs, pll_freq_tune_accum_init_mux, 0x17C);
|
||||
|
||||
struct mdp_intf_regs {
|
||||
uint32_t timing_eng_enable;
|
||||
uint32_t intf_config;
|
||||
uint32_t intf_hsync_ctl;
|
||||
uint32_t intf_vysnc_period_f0;
|
||||
uint32_t intf_vysnc_period_f1;
|
||||
uint32_t intf_vysnc_pulse_width_f0;
|
||||
uint32_t intf_vysnc_pulse_width_f1;
|
||||
uint32_t intf_disp_v_start_f0;
|
||||
uint32_t intf_disp_v_start_f1;
|
||||
uint32_t intf_disp_v_end_f0;
|
||||
uint32_t intf_disp_v_end_f1;
|
||||
uint32_t intf_active_v_start_f0;
|
||||
uint32_t intf_active_v_start_f1;
|
||||
uint32_t intf_active_v_end_f0;
|
||||
uint32_t intf_active_v_end_f1;
|
||||
uint32_t intf_disp_hctl;
|
||||
uint32_t intf_active_hctl;
|
||||
uint32_t intf_border_color;
|
||||
uint32_t intf_underflow_color;
|
||||
uint32_t hsync_skew;
|
||||
uint32_t polarity_ctl;
|
||||
uint32_t test_ctl;
|
||||
uint32_t tp_color0;
|
||||
uint32_t tp_color1;
|
||||
uint32_t intf_config2;
|
||||
uint32_t display_data_hctl;
|
||||
uint32_t reserved0[10];
|
||||
uint32_t intf_panel_format;
|
||||
uint32_t reserved1[55];
|
||||
uint32_t intf_prof_fetch_start;
|
||||
uint32_t reserved2[58];
|
||||
uint32_t intf_mux;
|
||||
};
|
||||
|
||||
check_member(mdp_intf_regs, intf_panel_format, 0x90);
|
||||
check_member(mdp_intf_regs, intf_prof_fetch_start, 0x170);
|
||||
check_member(mdp_intf_regs, intf_mux, 0x25C);
|
||||
|
||||
struct mdp_ctl_regs {
|
||||
uint32_t ctl_layer0;
|
||||
uint32_t ctl_layer1;
|
||||
uint32_t reserved0[3];
|
||||
uint32_t ctl_top;
|
||||
uint32_t ctl_flush;
|
||||
uint32_t ctl_start;
|
||||
uint32_t reserved1[53];
|
||||
uint32_t ctl_intf_active;
|
||||
uint32_t ctl_cdm_active;
|
||||
uint32_t ctl_fetch_pipe_active;
|
||||
uint32_t reserved2[4];
|
||||
uint32_t ctl_intf_flush;
|
||||
};
|
||||
|
||||
check_member(mdp_ctl_regs, ctl_top, 0x14);
|
||||
check_member(mdp_ctl_regs, ctl_intf_active, 0xF4);
|
||||
check_member(mdp_ctl_regs, ctl_intf_flush, 0x110);
|
||||
|
||||
struct mdp_layer_mixer_regs {
|
||||
uint32_t layer_op_mode;
|
||||
uint32_t layer_out_size;
|
||||
uint32_t layer_border_color_0;
|
||||
uint32_t layer_border_color_1;
|
||||
uint32_t reserved0[4];
|
||||
struct {
|
||||
uint32_t layer_blend_op;
|
||||
uint32_t layer_blend_const_alpha;
|
||||
uint32_t layer_blend_fg_color_fill_color0;
|
||||
uint32_t layer_blend_fg_color_fill_color1;
|
||||
uint32_t layer_blend_fg_fill_size;
|
||||
uint32_t layer_blend_fg_fill_xy;
|
||||
} layer_blend[6];
|
||||
};
|
||||
|
||||
struct mdp_sspp_regs {
|
||||
uint32_t sspp_src_size;
|
||||
uint32_t sspp_src_img_size;
|
||||
uint32_t sspp_src_xy;
|
||||
uint32_t sspp_out_size;
|
||||
uint32_t sspp_out_xy;
|
||||
uint32_t sspp_src0;
|
||||
uint32_t sspp_src1;
|
||||
uint32_t sspp_src2;
|
||||
uint32_t sspp_src3;
|
||||
uint32_t sspp_src_ystride0;
|
||||
uint32_t sspp_src_ystride1;
|
||||
uint32_t sspp_tile_frame_size;
|
||||
uint32_t sspp_src_format;
|
||||
uint32_t sspp_src_unpack_pattern;
|
||||
uint32_t sspp_src_op_mode;
|
||||
uint32_t reserved0[51];
|
||||
uint32_t sspp_sw_pic_ext_c0_req_pixels;
|
||||
uint32_t reserved1[3];
|
||||
uint32_t sspp_sw_pic_ext_c1c2_req_pixels;
|
||||
uint32_t reserved2[3];
|
||||
uint32_t sspp_sw_pic_ext_c3_req_pixels;
|
||||
};
|
||||
|
||||
check_member(mdp_sspp_regs, sspp_sw_pic_ext_c0_req_pixels, 0x108);
|
||||
check_member(mdp_sspp_regs, sspp_sw_pic_ext_c1c2_req_pixels, 0x118);
|
||||
check_member(mdp_sspp_regs, sspp_sw_pic_ext_c3_req_pixels, 0x128);
|
||||
|
||||
struct mdss_hw_regs {
|
||||
uint32_t hw_version;
|
||||
};
|
||||
|
||||
struct vbif_rt_regs {
|
||||
uint32_t reserved0[88];
|
||||
uint32_t vbif_out_axi_amemtype_conf0;
|
||||
uint32_t vbif_out_axi_amemtype_conf1;
|
||||
uint32_t reserved1[250];
|
||||
struct {
|
||||
uint32_t vbif_xinl_qos_rp_remap;
|
||||
uint32_t vbif_xinh_qos_rp_remap;
|
||||
} qos_rp_remap[8];
|
||||
struct {
|
||||
uint32_t vbif_xinl_qos_lvl_remap;
|
||||
uint32_t vbif_xinh_qos_lvl_remap;
|
||||
} qos_lvl_remap[8];
|
||||
};
|
||||
|
||||
check_member(vbif_rt_regs, vbif_out_axi_amemtype_conf0, 0x160);
|
||||
check_member(vbif_rt_regs, qos_rp_remap[0], 0x550);
|
||||
|
||||
enum {
|
||||
MDSS_BASE = 0xAE00000,
|
||||
};
|
||||
|
||||
enum {
|
||||
MDP_0_CTL_BASE = MDSS_BASE + 0x16000,
|
||||
MDP_VP_0_SSPP_BASE = MDSS_BASE + 0x5000,
|
||||
MDP_VP_0_LAYER_MIXER_BASE = MDSS_BASE + 0x45000,
|
||||
MDP_5_INTF_BASE = MDSS_BASE + 0x3A000,
|
||||
MDP_VBIF_RT_BASE = MDSS_BASE + 0xB0000,
|
||||
DSI0_CTL_BASE = MDSS_BASE + 0x94000,
|
||||
DSI0_PHY_BASE = MDSS_BASE + 0x94400,
|
||||
DSI0_PHY_DLN0_BASE = MDSS_BASE + 0x94600,
|
||||
DSI0_PHY_DLN1_BASE = MDSS_BASE + 0x94680,
|
||||
DSI0_PHY_DLN2_BASE = MDSS_BASE + 0x94700,
|
||||
DSI0_PHY_DLN3_BASE = MDSS_BASE + 0x94780,
|
||||
DSI0_PHY_CLKLN_BASE = MDSS_BASE + 0x94800,
|
||||
DSI0_PHY_PLL_QLINK_COM = MDSS_BASE + 0x94a00,
|
||||
};
|
||||
|
||||
/* DSI_0_CLK_CTRL */
|
||||
enum {
|
||||
INTF = BIT(31),
|
||||
PERIPH = BIT(30),
|
||||
CWB = BIT(28),
|
||||
ROT = BIT(27),
|
||||
CDM_0 = BIT(26),
|
||||
DMA_3 = BIT(25),
|
||||
DMA_2 = BIT(24),
|
||||
MERGE_3D = BIT(23),
|
||||
DSC = BIT(22),
|
||||
DSPP_3 = BIT(21),
|
||||
LAYER_MIXER_5 = BIT(20),
|
||||
DSPP_PA_LUTV_3 = BIT(19),
|
||||
VIG_3 = BIT(18),
|
||||
CTL = BIT(17),
|
||||
WB = BIT(16),
|
||||
DSPP_2 = BIT(15),
|
||||
DSPP_1 = BIT(14),
|
||||
DSPP_0 = BIT(13),
|
||||
DMA_1 = BIT(12),
|
||||
DMA_0 = BIT(11),
|
||||
LAYER_MIXER_4 = BIT(10),
|
||||
LAYER_MIXER_3 = BIT(9),
|
||||
LAYER_MIXER_2 = BIT(8),
|
||||
LAYER_MIXER_1 = BIT(7),
|
||||
LAYER_MIXER_0 = BIT(6),
|
||||
DSPP_PA_LUTV_2 = BIT(5),
|
||||
DSPP_PA_LUTV_1 = BIT(4),
|
||||
DSPP_PA_LUTV_0 = BIT(3),
|
||||
VIG_2 = BIT(2),
|
||||
VIG_1 = BIT(1),
|
||||
VIG_0 = BIT(0),
|
||||
};
|
||||
|
||||
enum {
|
||||
DSI_AHBS_HCLK_ON = BIT(0),
|
||||
DSI_AHBM_SCLK_ON = BIT(1),
|
||||
DSI_PCLK_ON = BIT(2),
|
||||
DSI_DSICLK_ON = BIT(3),
|
||||
DSI_BYTECLK_ON = BIT(4),
|
||||
DSI_ESCCLK_ON = BIT(5),
|
||||
DSI_FORCE_ON_DYN_AHBS_HCLK = BIT(8),
|
||||
DSI_FORCE_ON_DYN_AHBM_HCLK = BIT(9),
|
||||
DSI_FORCE_ON_DYN_DSICLK = BIT(10),
|
||||
DSI_FORCE_ON_DYN_BYTECLK = BIT(11),
|
||||
DSI_AHBS_HCLK_HYSTERISIS1_CTRL = (3 << 11),
|
||||
DSI_AHBM_HCLK_HYSTERISIS1_CTRL = (3 << 13),
|
||||
DSI_DSICLK_HYSTERISIS1_CTRL = (3 << 15),
|
||||
DSI_FORCE_ON_DYN_PCLK = BIT(20),
|
||||
DSI_FORCE_ON_LANE_LAYER_TG_BYTECLK = BIT(21),
|
||||
DSI_DMA_CLK_STOP = BIT(22),
|
||||
};
|
||||
|
||||
/* DSI_0_INT_CTRL */
|
||||
enum {
|
||||
DSI_CMD_MODE_DMA_DONE_AK = BIT(0),
|
||||
DSI_CMD_MODE_DMA_DONE_STAT = BIT(0),
|
||||
DSI_CMD_MODE_DMA_DONE_MASK = BIT(1),
|
||||
DSI_CMD_MODE_MDP_DONE_AK = BIT(8),
|
||||
DSI_CMD_MODE_MDP_DONE_STAT = BIT(8),
|
||||
DSI_CMD_MODE_MDP_DONE_MASK = BIT(9),
|
||||
DSI_CMD_MDP_STREAM0_DONE_AK = BIT(10),
|
||||
DSI_CMD_MDP_STREAM0_DONE_STAT = BIT(10),
|
||||
DSI_CMD_MDP_STREAM0_DONE_MASK = BIT(11),
|
||||
DSI_VIDEO_MODE_DONE_AK = BIT(16),
|
||||
DSI_VIDEO_MODE_DONE_STAT = BIT(16),
|
||||
DSI_VIDEO_MODE_DONE_MASK = BIT(17),
|
||||
DSI_BTA_DONE_AK = BIT(20),
|
||||
DSI_BTA_DONE_STAT = BIT(20),
|
||||
DSI_BTA_DONE_MASK = BIT(21),
|
||||
DSI_ERROR_AK = BIT(24),
|
||||
DSI_ERROR_STAT = BIT(24),
|
||||
DSI_ERROR_MASK = BIT(25),
|
||||
DSI_DYNAMIC_BLANKING_DMA_DONE_AK = BIT(26),
|
||||
DSI_DYNAMIC_BLANKING_DMA_DONE_STAT = BIT(26),
|
||||
DSI_DYNAMIC_BLANKING_DMA_DONE_MASK = BIT(27),
|
||||
DSI_DYNAMIC_REFRESH_DONE_AK = BIT(28),
|
||||
DSI_DYNAMIC_REFRESH_DONE_STAT = BIT(28),
|
||||
DSI_DYNAMIC_REFRESH_DONE_MASK = BIT(29),
|
||||
DSI_DESKEW_DONE_AK = BIT(30),
|
||||
DSI_DESKEW_DONE_STAT = BIT(30),
|
||||
DSI_DESKEW_DONE_MASK = BIT(31),
|
||||
};
|
||||
|
||||
/* DSI_0_COMMAND_MODE_MDP_DCS_CMD_CTRL */
|
||||
enum {
|
||||
WR_MEM_START = 255,
|
||||
WR_MEM_CONTINUE = 255 << 8,
|
||||
INSERT_DCS_COMMAND = BIT(16),
|
||||
};
|
||||
|
||||
/* DSI_0_COMMAND_MODE_DMA_CTRL */
|
||||
enum {
|
||||
PACKET_TYPE = BIT(24),
|
||||
POWER_MODE = BIT(26),
|
||||
EMBEDDED_MODE = BIT(28),
|
||||
WC_SEL = BIT(29),
|
||||
BROADCAST_MASTER = BIT(30),
|
||||
BROADCAST_EN = BIT(31),
|
||||
};
|
||||
|
||||
/* MDP_VP_0_VIG_0_SSPP_SRC_OP_MODE */
|
||||
enum {
|
||||
BWC_DEC_EN = BIT(0),
|
||||
SW_PIX_EXT_OVERRIDE = BIT(31),
|
||||
};
|
||||
|
||||
/* MDP_INTF_x_INTF_CONFIG */
|
||||
enum {
|
||||
INTERLACE_MODE = BIT(0),
|
||||
REPEAT_PIXEL = BIT(1),
|
||||
INTERLACE_INIT_SEL = BIT(2),
|
||||
BORDER_ENABLE = BIT(3),
|
||||
EDP_PSR_OVERRIDE_EN = BIT(7),
|
||||
PACK_ALIGN = BIT(10),
|
||||
DSI_VIDEO_STOP_MODE = BIT(23),
|
||||
ACTIVE_H_EN = BIT(29),
|
||||
ACTIVE_V_EN = BIT(30),
|
||||
PROG_FETCH_START_EN = BIT(31),
|
||||
};
|
||||
|
||||
/* MDP_CTL_0_LAYER_0 */
|
||||
enum {
|
||||
VIG_0_OUT = BIT(0),
|
||||
BORDER_OUT = BIT(24),
|
||||
};
|
||||
|
||||
/* MDP_CTL_0_FETCH_PIPE_ACTIVE */
|
||||
enum {
|
||||
FETCH_PIPE_VIG0_ACTIVE = BIT(16),
|
||||
FETCH_PIPE_VIG1_ACTIVE = BIT(17),
|
||||
};
|
||||
|
||||
/* MDP_CTL_0_INTF_ACTIVE*/
|
||||
enum {
|
||||
INTF_ACTIVE_0 = BIT(0),
|
||||
INTF_ACTIVE_1 = BIT(1),
|
||||
INTF_ACTIVE_5 = BIT(5),
|
||||
};
|
||||
|
||||
/* MDP_CTL_0_INTF_FLUSH */
|
||||
enum {
|
||||
INTF_FLUSH_0 = BIT(0),
|
||||
INTF_FLUSH_1 = BIT(1),
|
||||
INTF_FLUSH_5 = BIT(5),
|
||||
};
|
||||
|
||||
static struct dsi_regs *const dsi0 = (void *)DSI0_CTL_BASE;
|
||||
static struct dsi_phy_regs *const dsi0_phy = (void *)DSI0_PHY_BASE;
|
||||
static struct dsi_phy_pll_qlink_regs *const phy_pll_qlink = (void *)DSI0_PHY_PLL_QLINK_COM;
|
||||
static struct mdss_hw_regs *const mdss_hw = (void *)MDSS_BASE;
|
||||
static struct mdp_intf_regs *const mdp_intf = (void *)MDP_5_INTF_BASE;
|
||||
static struct mdp_ctl_regs *const mdp_ctl = (void *)MDP_0_CTL_BASE;
|
||||
static struct mdp_layer_mixer_regs *const mdp_layer_mixer = (void *)MDP_VP_0_LAYER_MIXER_BASE;
|
||||
static struct mdp_sspp_regs *const mdp_sspp = (void *)MDP_VP_0_SSPP_BASE;
|
||||
static struct vbif_rt_regs *const vbif_rt = (void *)MDP_VBIF_RT_BASE;
|
||||
|
||||
void mdss_intf_tg_setup(struct edid *edid);
|
||||
void mdp_dsi_video_config(struct edid *edid);
|
||||
void mdp_dsi_video_on(void);
|
||||
void enable_mdss_clk(void);
|
||||
void mdss_ctrl_config(void);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue