GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/skylake: Use PEG definitions from pci_devs.h 

Change-Id: I7114deed35f25e74ac508f08e9c85653a7fe39ed
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This commit is contained in:
Felix Singer 2020-08-11 06:52:07 +02:00 committed by Michael Niewöhner
parent e1528fe358
commit 4e9687c416
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/intel/skylake/romstage/romstage.c
View File

@ -170,7 +170,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
* If PEG port is not defined in the device tree, it will be disabled
* in FSP
*/
dev = pcidev_on_root(SA_DEV_SLOT_PEG, 0); /* PEG 0:1:0 */
dev = pcidev_path_on_root(SA_DEVFN_PEG0); /* PEG 0:1:0 */
if (!dev || !dev->enabled)
m_cfg->Peg0Enable = 0;
else if (dev->enabled) {
@ -185,7 +185,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
m_t_cfg->Peg0Gen3EqPh3Method = 0;
}
dev = pcidev_on_root(SA_DEV_SLOT_PEG, 1); /* PEG 0:1:1 */
dev = pcidev_path_on_root(SA_DEVFN_PEG1); /* PEG 0:1:1 */
if (!dev || !dev->enabled)
m_cfg->Peg1Enable = 0;
else if (dev->enabled) {
@ -197,7 +197,7 @@ static void soc_peg_init_params(FSP_M_CONFIG *m_cfg,
m_t_cfg->Peg1Gen3EqPh3Method = 0;
}
dev = pcidev_on_root(SA_DEV_SLOT_PEG, 2); /* PEG 0:1:2 */
dev = pcidev_path_on_root(SA_DEVFN_PEG2); /* PEG 0:1:2 */
if (!dev || !dev->enabled)
m_cfg->Peg2Enable = 0;
else if (dev->enabled) {