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Rename ECAM-specific MMCONF Kconfigs 

Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space.  Some platforms have a different way of mapping the PCI config
space to memory.  This patch renames the following configs to
make it clear that these configs are ECAM-specific:

- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH

Please refer to CB:57861 "Proposed coreboot Changes" for more
details.

BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
     Make sure Jenkins verifies that builds on other boards

Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Shelley Chen 2021-10-20 15:43:45 -07:00
parent 5c163bb869
commit 4e9bb3308e
104 changed files with 205 additions and 194 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
payloads/external/Makefile.inc vendored
View File

@ -146,7 +146,7 @@ payloads/external/tianocore/tianocore/Build/UEFIPAYLOAD.fd tianocore: $(DOTCONFI
CONFIG_TIANOCORE_BOOTSPLASH_FILE=$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \
CONFIG_TIANOCORE_UEFIPAYLOAD=$(CONFIG_TIANOCORE_UEFIPAYLOAD) \
CONFIG_TIANOCORE_UPSTREAM=$(CONFIG_TIANOCORE_UPSTREAM) \
CONFIG_MMCONF_BASE_ADDRESS=$(CONFIG_MMCONF_BASE_ADDRESS) \
CONFIG_ECAM_MMCONF_BASE_ADDRESS=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) \
CONFIG_TIANOCORE_ABOVE_4G_MEMORY=$(CONFIG_TIANOCORE_ABOVE_4G_MEMORY) \
CONFIG_TIANOCORE_BOOT_TIMEOUT=$(CONFIG_TIANOCORE_BOOT_TIMEOUT) \
CONFIG_TIANOCORE_CBMEM_LOGGING=$(CONFIG_TIANOCORE_CBMEM_LOGGING) \

2
payloads/external/tianocore/Makefile vendored
View File

@ -9,7 +9,7 @@ project_git_repo=https://github.com/mrchromebox/edk2
project_git_branch=uefipayload_202107
upstream_git_repo=https://github.com/tianocore/edk2
build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
build_flavor=-D BOOTLOADER=COREBOOT -D PCIE_BASE=$(CONFIG_ECAM_MMCONF_BASE_ADDRESS) -DPS2_KEYBOARD_ENABLE
ifeq ($(CONFIG_TIANOCORE_COREBOOTPAYLOAD),y)
project_git_branch=coreboot_fb

5
src/acpi/acpi.c
View File

@ -266,7 +266,8 @@ void acpi_create_madt(acpi_madt_t *madt)
static unsigned long acpi_fill_mcfg(unsigned long current)
{
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current,
CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1);
CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0,
CONFIG_ECAM_MMCONF_BUS_NUMBER - 1);
return current;
}
@ -291,7 +292,7 @@ void acpi_create_mcfg(acpi_mcfg_t *mcfg)
header->length = sizeof(acpi_mcfg_t);
header->revision = get_acpi_table_revision(MCFG);
if (CONFIG(MMCONF_SUPPORT))
if (CONFIG(ECAM_MMCONF_SUPPORT))
current = acpi_fill_mcfg(current);
/* (Re)calculate length and checksum. */

6
src/acpi/dsdt_top.asl
View File

@ -31,13 +31,13 @@ Method (_PIC, 1)
PICM = Arg0
}
#if CONFIG(MMCONF_SUPPORT)
#if CONFIG(ECAM_MMCONF_SUPPORT)
Scope(\_SB) {
/* Base address of PCIe config space */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
Name(PCBA, CONFIG_ECAM_MMCONF_BASE_ADDRESS)
/* Length of PCIe config space, 1MB each bus */
Name(PCLN, CONFIG_MMCONF_LENGTH)
Name(PCLN, CONFIG_ECAM_MMCONF_LENGTH)
/* PCIe Configuration Space */
OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */

2
src/arch/x86/include/arch/pci_io_cfg.h
View File

@ -69,7 +69,7 @@ void pci_io_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value)
outl(value, 0xCFC);
}
#if !CONFIG(MMCONF_SUPPORT)
#if !CONFIG(ECAM_MMCONF_SUPPORT)
/* Avoid name collisions as different stages have different signature
* for these functions. The _s_ stands for simple, fundamental IO or

2
src/arch/x86/include/arch/pci_ops.h
View File

@ -4,7 +4,7 @@
#define ARCH_I386_PCI_OPS_H
#include <arch/pci_io_cfg.h>
#if CONFIG(MMCONF_SUPPORT)
#if CONFIG(ECAM_MMCONF_SUPPORT)
#include <device/pci_mmio_cfg.h>
#endif

38
src/device/Kconfig
View File

@ -499,13 +499,21 @@ config PCI
if PCI
config NO_MMCONF_SUPPORT
config NO_ECAM_MMCONF_SUPPORT
bool
default n
help
Disable the use of the Enhanced Configuration
Access mechanism (ECAM) method for accessing PCI config
address space.
config MMCONF_SUPPORT
config ECAM_MMCONF_SUPPORT
bool
default !NO_MMCONF_SUPPORT
default !NO_ECAM_MMCONF_SUPPORT
help
Enable the use of the Enhanced Configuration
Access mechanism (ECAM) method for accessing PCI config
address space.
config PCIX_PLUGIN_SUPPORT
bool
@ -540,20 +548,20 @@ config PCIEXP_PLUGIN_SUPPORT
bool
default y
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
hex
depends on MMCONF_SUPPORT
depends on ECAM_MMCONF_SUPPORT
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
depends on MMCONF_SUPPORT
depends on ECAM_MMCONF_SUPPORT
config MMCONF_LENGTH
config ECAM_MMCONF_LENGTH
hex
depends on MMCONF_SUPPORT
default 0x04000000 if MMCONF_BUS_NUMBER = 64
default 0x08000000 if MMCONF_BUS_NUMBER = 128
default 0x10000000 if MMCONF_BUS_NUMBER = 256
depends on ECAM_MMCONF_SUPPORT
default 0x04000000 if ECAM_MMCONF_BUS_NUMBER = 64
default 0x08000000 if ECAM_MMCONF_BUS_NUMBER = 128
default 0x10000000 if ECAM_MMCONF_BUS_NUMBER = 256
default 0x0
config PCI_ALLOW_BUS_MASTER
@ -619,7 +627,7 @@ config PCIEXP_CLK_PM
config PCIEXP_L1_SUB_STATE
prompt "Enable PCIe ASPM L1 SubState"
bool
depends on (MMCONF_SUPPORT || PCI_IO_CFG_EXT)
depends on (ECAM_MMCONF_SUPPORT || PCI_IO_CFG_EXT)
default n
help
Detect and enable ASPM on PCIe links.
@ -635,8 +643,8 @@ if PCIEXP_HOTPLUG
config PCIEXP_HOTPLUG_BUSES
int "PCI Express Hotplug Buses"
default 8 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 64
default 16 if MMCONF_SUPPORT && MMCONF_BUS_NUMBER <= 128
default 8 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 64
default 16 if ECAM_MMCONF_SUPPORT && ECAM_MMCONF_BUS_NUMBER <= 128
default 32
help
This is the number of buses allocated for hotplug PCI express

4
src/device/device_util.c
View File

@ -857,8 +857,8 @@ void fixed_io_resource(struct device *dev, unsigned long index,
void mmconf_resource(struct device *dev, unsigned long index)
{
struct resource *resource = new_resource(dev, index);
resource->base = CONFIG_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_MMCONF_LENGTH;
resource->base = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
resource->size = CONFIG_ECAM_MMCONF_LENGTH;
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;

2
src/device/pci_ops.c
View File

@ -7,7 +7,7 @@
#include <device/pci_ops.h>
#include <device/pci_type.h>
u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS;
u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS;
/**
* Given a device, a capability type, and a last position, return the next

6
src/drivers/intel/fsp1_1/romstage.c
View File

@ -103,9 +103,9 @@ void cache_as_ram_stage_main(FSP_INFO_HEADER *fih)
timestamp_add_now(TS_START_ROMSTAGE);
/* Display parameters */
if (!CONFIG(NO_MMCONF_SUPPORT))
printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
CONFIG_MMCONF_BASE_ADDRESS);
if (!CONFIG(NO_ECAM_MMCONF_SUPPORT))
printk(BIOS_SPEW, "CONFIG_ECAM_MMCONF_BASE_ADDRESS: 0x%08x\n",
CONFIG_ECAM_MMCONF_BASE_ADDRESS);
printk(BIOS_INFO, "Using FSP 1.1\n");
/* Display FSP banner */

12
src/include/device/pci_mmio_cfg.h
View File

@ -25,17 +25,17 @@ union pci_bank {
uint32_t reg32[4096 / sizeof(uint32_t)];
};
#if CONFIG(MMCONF_SUPPORT)
#if CONFIG(ECAM_MMCONF_SUPPORT)
#if CONFIG_MMCONF_BASE_ADDRESS == 0
#error "CONFIG_MMCONF_BASE_ADDRESS undefined!"
#if CONFIG_ECAM_MMCONF_BASE_ADDRESS == 0
#error "CONFIG_ECAM_MMCONF_BASE_ADDRESS undefined!"
#endif
#if CONFIG_MMCONF_BUS_NUMBER * MiB != CONFIG_MMCONF_LENGTH
#error "CONFIG_MMCONF_LENGTH does not correspond with CONFIG_MMCONF_BUS_NUMBER!"
#if CONFIG_ECAM_MMCONF_BUS_NUMBER * MiB != CONFIG_ECAM_MMCONF_LENGTH
#error "CONFIG_ECAM_MMCONF_LENGTH does not correspond with CONFIG_ECAM_MMCONF_BUS_NUMBER!"
#endif
/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we
/* By not assigning this to CONFIG_ECAM_MMCONF_BASE_ADDRESS here we
prevent some sub-optimal constant folding. */
extern u8 *const pci_mmconf;

2
src/lib/Kconfig
View File

@ -70,7 +70,7 @@ config HWBASE_DYNAMIC_MMIO
config HWBASE_DEFAULT_MMCONF
hex
default MMCONF_BASE_ADDRESS
default ECAM_MMCONF_BASE_ADDRESS
config HWBASE_DIRECT_PCIDEV
def_bool y

2
src/mainboard/asus/p8x7x-series/variants/p8z77-m_pro/early_init.c
View File

@ -85,7 +85,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/emulation/qemu-i440fx/Kconfig
View File

@ -3,7 +3,7 @@ if BOARD_EMULATION_QEMU_X86_I440FX
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_QEMU_X86
select NO_MMCONF_SUPPORT
select NO_ECAM_MMCONF_SUPPORT
select SOUTHBRIDGE_INTEL_I82371EB
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT

4
src/mainboard/emulation/qemu-q35/Kconfig
View File

@ -56,10 +56,10 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "QEMU x86 q35/ich9"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xb0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 256

4
src/mainboard/emulation/qemu-q35/bootblock.c
View File

@ -11,12 +11,12 @@ static void bootblock_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to
* setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to
* to true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.

4
src/mainboard/emulation/qemu-q35/memmap.c
View File

@ -14,7 +14,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@ -24,7 +24,7 @@ static uint32_t encode_pciexbar_length(void)
uint32_t make_pciexbar(void)
{
return CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
return CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
}
/* Check that MCFG is active. If it's not, QEMU was started for machine PC */

2
src/mainboard/google/butterfly/early_init.c
View File

@ -79,7 +79,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/google/link/early_init.c
View File

@ -88,7 +88,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/google/parrot/early_init.c
View File

@ -57,7 +57,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/google/stout/early_init.c
View File

@ -94,7 +94,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/intel/dcp847ske/romstage.c
View File

@ -17,7 +17,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/intel/emeraldlake2/early_init.c
View File

@ -54,7 +54,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/kontron/ktqm77/early_init.c
View File

@ -59,7 +59,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/lenovo/x220/early_init.c
View File

@ -15,7 +15,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/roda/rv11/variants/rv11/early_init.c
View File

@ -13,7 +13,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/roda/rv11/variants/rw11/early_init.c
View File

@ -43,7 +43,7 @@ void mainboard_fill_pei_data(struct pei_data *const pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/samsung/lumpy/early_init.c
View File

@ -119,7 +119,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

2
src/mainboard/samsung/stumpy/early_init.c
View File

@ -104,7 +104,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,

4
src/northbridge/amd/agesa/family14/Kconfig
View File

@ -11,10 +11,10 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
endif # NORTHBRIDGE_AMD_AGESA_FAMILY14

4
src/northbridge/amd/agesa/family15tn/Kconfig
View File

@ -11,10 +11,10 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_TN

4
src/northbridge/amd/agesa/family16kb/Kconfig
View File

@ -11,10 +11,10 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID

4
src/northbridge/amd/pi/00730F01/Kconfig
View File

@ -10,10 +10,10 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x100000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID

2
src/northbridge/intel/e7505/Kconfig
View File

@ -7,7 +7,7 @@ if NORTHBRIDGE_INTEL_E7505
config NORTHBRIDGE_SPECIFIC_OPTIONS
def_bool y
select NO_MMCONF_SUPPORT
select NO_ECAM_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
select NO_CBFS_MCACHE
select LEGACY_SMP_INIT

4
src/northbridge/intel/gm45/Kconfig
View File

@ -23,10 +23,10 @@ config VGA_BIOS_ID
string
default "8086,2a42"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 64

2
src/northbridge/intel/gm45/acpi/gm45.asl
View File

@ -16,7 +16,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

8
src/northbridge/intel/gm45/bootblock.c
View File

@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@ -21,17 +21,17 @@ void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to
* setup the PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to
* setup the PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to
* true. That way all subsequent non-explicit config accesses use
* MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final
* assumption is that no assembly code is using the
* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under
* 4GiB.
*/
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0);
pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
}

4
src/northbridge/intel/haswell/Kconfig
View File

@ -32,10 +32,10 @@ config VGA_BIOS_ID
string
default "8086,0166"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 64

6
src/northbridge/intel/haswell/acpi/hostbridge.asl
View File

@ -125,7 +125,7 @@ Name (MCRS, ResourceTemplate()
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
// PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@ -161,7 +161,7 @@ Method (_CRS, 0, Serialized)
}
PMIN = Local0
PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
PLEN = (PMAX - PMIN) + 1
Return (MCRS)
@ -178,7 +178,7 @@ Device (PDRC)
Memory32Fixed (ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, MCH_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, DMI_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, EP_BASE_SIZE)
Memory32Fixed (ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed (ReadWrite, 0xfed20000, 0x00020000) // TXT
Memory32Fixed (ReadWrite, 0xfed40000, 0x00005000) // TPM
Memory32Fixed (ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

8
src/northbridge/intel/haswell/bootblock.c
View File

@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@ -21,15 +21,15 @@ void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
* PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the
* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}

2
src/northbridge/intel/haswell/haswell_mrc/raminit.c
View File

@ -349,7 +349,7 @@ void perform_raminit(const int s3resume)
.mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE,
.dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE,
.epbar = CONFIG_FIXED_EPBAR_MMIO_BASE,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
.pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS,
.smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.hpet_address = CONFIG_HPET_ADDRESS,
.rcba = CONFIG_FIXED_RCBA_MMIO_BASE,

2
src/northbridge/intel/i440bx/Kconfig
View File

@ -2,7 +2,7 @@
config NORTHBRIDGE_INTEL_I440BX
bool
select NO_MMCONF_SUPPORT
select NO_ECAM_MMCONF_SUPPORT
select HAVE_DEBUG_RAM_SETUP
select NO_CBFS_MCACHE
select LEGACY_SMP_INIT

4
src/northbridge/intel/i945/Kconfig
View File

@ -35,10 +35,10 @@ config I945_LVDS
for the LVDS port. A linear framebuffer is only supported for
LVDS.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 64

2
src/northbridge/intel/i945/acpi/i945.asl
View File

@ -40,7 +40,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

16
src/northbridge/intel/i945/bootblock.c
View File

@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@ -20,14 +20,16 @@ static uint32_t encode_pciexbar_length(void)
void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
* because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit
* config accesses use MCFG. This code also assumes that bootblock_northbridge_init() is
* the first thing called in the non-asm boot block code. The final assumption is that
* no assembly code is using the CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way
* all subsequent non-explicit config accesses use MCFG. This code also
* assumes that bootblock_northbridge_init() is the first thing called
* in the non-asm boot block code. The final assumption is that no
* assembly code is using the CONFIG(ECAM_MMCONF_SUPPORT) option to do
* PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}

4
src/northbridge/intel/ironlake/Kconfig
View File

@ -39,10 +39,10 @@ config DCACHE_BSP_STACK_SIZE
The amount of anticipated stack usage in CAR by bootblock and
other stages.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 256
config INTEL_GMA_BCLV_OFFSET

2
src/northbridge/intel/ironlake/acpi/ironlake.asl
View File

@ -14,7 +14,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00008000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

4
src/northbridge/intel/ironlake/bootblock.c
View File

@ -10,7 +10,7 @@
static uint32_t encode_pciexbar_length(void)
{
/* NOTE: Ironlake uses a different encoding for the PCIEXBAR length field */
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 6 << 1;
case 64: return 7 << 1;
@ -27,7 +27,7 @@ void bootblock_early_northbridge_init(void)
*/
const pci_devfn_t qpi_sad = PCI_DEV(255, 0, 1);
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(qpi_sad, SAD_PCIEXBAR + 4, 0);
pci_io_write_config32(qpi_sad, SAD_PCIEXBAR, reg32);
}

2
src/northbridge/intel/ironlake/ironlake.h
View File

@ -21,7 +21,7 @@
#include "memmap.h"
#define QUICKPATH_BUS (CONFIG_MMCONF_BUS_NUMBER - 1)
#define QUICKPATH_BUS (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1)
#include <southbridge/intel/ibexpeak/pch.h>

4
src/northbridge/intel/pineview/Kconfig
View File

@ -19,10 +19,10 @@ config VGA_BIOS_ID
string
default "8086,a001"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 256

2
src/northbridge/intel/pineview/acpi/pineview.asl
View File

@ -15,7 +15,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */

4
src/northbridge/intel/pineview/bootblock.c
View File

@ -8,7 +8,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@ -18,6 +18,6 @@ static uint32_t encode_pciexbar_length(void)
void bootblock_early_northbridge_init(void)
{
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}

4
src/northbridge/intel/sandybridge/Kconfig
View File

@ -83,12 +83,12 @@ config VGA_BIOS_ID
string
default "8086,0106"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
help
The MRC blob requires it to be at 0xf0000000.
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 64

4
src/northbridge/intel/sandybridge/acpi/hostbridge.asl
View File

@ -320,7 +320,7 @@ Name (MCRS, ResourceTemplate()
0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
0x00010000,,, FSEG)
// PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS)
// PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@ -356,7 +356,7 @@ Method (_CRS, 0, Serialized)
}
PMIN = Local0
PMAX = CONFIG_MMCONF_BASE_ADDRESS - 1
PMAX = CONFIG_ECAM_MMCONF_BASE_ADDRESS - 1
PLEN = PMAX - PMIN + 1
Return (MCRS)

8
src/northbridge/intel/sandybridge/bootblock.c
View File

@ -9,7 +9,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@ -21,15 +21,15 @@ void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
* PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the
* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg32);
}

2
src/northbridge/intel/sandybridge/raminit_mrc.c
View File

@ -231,7 +231,7 @@ static void northbridge_fill_pei_data(struct pei_data *pei_data)
pei_data->mchbar = CONFIG_FIXED_MCHBAR_MMIO_BASE;
pei_data->dmibar = CONFIG_FIXED_DMIBAR_MMIO_BASE;
pei_data->epbar = CONFIG_FIXED_EPBAR_MMIO_BASE;
pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
pei_data->hpet_address = CONFIG_HPET_ADDRESS;
pei_data->thermalbase = 0xfed08000;
pei_data->system_type = !(get_platform_type() == PLATFORM_MOBILE);

4
src/northbridge/intel/x4x/Kconfig
View File

@ -21,10 +21,10 @@ config VGA_BIOS_ID
string
default "8086,2e32"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 256

2
src/northbridge/intel/x4x/acpi/x4x.asl
View File

@ -13,7 +13,7 @@ Device (PDRC)
Memory32Fixed(ReadWrite, CONFIG_FIXED_MCHBAR_MMIO_BASE, 0x00004000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_DMIBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_FIXED_EPBAR_MMIO_BASE, 0x00001000)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH

4
src/northbridge/intel/x4x/bootblock.c
View File

@ -10,7 +10,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@ -23,6 +23,6 @@ void bootblock_early_northbridge_init(void)
/* Disable LaGrande Technology (LT) */
read32((void *)TPM_BASE_ADDRESS);
const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);
}

4
src/security/intel/stm/StmPlatformResource.c
View File

@ -98,8 +98,8 @@ MSR_TABLE_ENTRY msr_table[] = {
static void fixup_pciex_resource(void)
{
// Find max bus number and PCIEX length
rsc_pcie_mmio.length = CONFIG_MMCONF_LENGTH; // 0x10000000;// 256 MB
rsc_pcie_mmio.base = CONFIG_MMCONF_BASE_ADDRESS;
rsc_pcie_mmio.length = CONFIG_ECAM_MMCONF_LENGTH; // 0x10000000;// 256 MB
rsc_pcie_mmio.base = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
}
/*

4
src/soc/amd/cezanne/Kconfig
View File

@ -216,10 +216,10 @@ config RO_REGION_ONLY
depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
default "apu/amdfw"
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
config MAX_CPUS

6
src/soc/amd/cezanne/acpi/pci0.asl
View File

@ -66,14 +66,14 @@ Device(PCI0) {
/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
MM1B = TOM1
Local0 = CONFIG_MMCONF_BASE_ADDRESS
Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
Local0 -= TOM1
MM1L = Local0
CreateWordField(CRES, ^PSB0._MAX, BMAX)
CreateWordField(CRES, ^PSB0._LEN, BLEN)
BMAX = CONFIG_MMCONF_BUS_NUMBER - 1
BLEN = CONFIG_MMCONF_BUS_NUMBER
BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */

2
src/soc/amd/cezanne/fsp_m_params.c
View File

@ -70,7 +70,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);

4
src/soc/amd/common/block/pci/amd_pci_mmconf.c
View File

@ -10,7 +10,7 @@ void enable_pci_mmconf(void)
msr_t mmconf;
mmconf.hi = 0;
mmconf.lo = CONFIG_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
| fms(CONFIG_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
mmconf.lo = CONFIG_ECAM_MMCONF_BASE_ADDRESS | MMIO_RANGE_EN
| fms(CONFIG_ECAM_MMCONF_BUS_NUMBER) << MMIO_BUS_RANGE_SHIFT;
wrmsr(MMIO_CONF_BASE, mmconf);
}

4
src/soc/amd/picasso/Kconfig
View File

@ -200,10 +200,10 @@ config RAMBASE
hex
default 0x10000000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
config VERSTAGE_ADDR

6
src/soc/amd/picasso/acpi/sb_pci0_fch.asl
View File

@ -73,14 +73,14 @@ Method(_CRS, 0) {
/* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */
MM1B = TOM1
Local0 = CONFIG_MMCONF_BASE_ADDRESS
Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS
Local0 -= TOM1
MM1L = Local0
CreateWordField(CRES, ^PSB0._MAX, BMAX)
CreateWordField(CRES, ^PSB0._LEN, BLEN)
BMAX = CONFIG_MMCONF_BUS_NUMBER - 1
BLEN = CONFIG_MMCONF_BUS_NUMBER
BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1
BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER
Return(CRES) /* note to change the Name buffer */
} /* end of Method(_SB.PCI0._CRS) */

2
src/soc/amd/picasso/fsp_m_params.c
View File

@ -19,7 +19,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
mcfg->pci_express_base_addr = CONFIG_MMCONF_BASE_ADDRESS;
mcfg->pci_express_base_addr = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
mcfg->tseg_size = CONFIG_SMM_TSEG_SIZE;
mcfg->serial_port_base = uart_platform_base(CONFIG_UART_FOR_CONSOLE);
mcfg->serial_port_use_mmio = CONFIG(DRIVERS_UART_8250MEM);

4
src/soc/amd/stoneyridge/Kconfig
View File

@ -120,10 +120,10 @@ config BOTTOMIO_POSITION
option is useful when PCI peripherals requesting large address
ranges are present.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xF8000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID

4
src/soc/cavium/cn81xx/Kconfig
View File

@ -9,7 +9,7 @@ config SOC_CAVIUM_CN81XX
select UART_OVERRIDE_REFCLK
select SOC_CAVIUM_COMMON
select CAVIUM_BDK_DDR_TUNE_HW_OFFSETS
select MMCONF_SUPPORT
select ECAM_MMCONF_SUPPORT
select PCI
if SOC_CAVIUM_CN81XX
@ -36,7 +36,7 @@ config HEAP_SIZE
config STACK_SIZE
default 0x2000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0x848000000000
endif

2
src/soc/example/min86/Kconfig
View File

@ -16,7 +16,7 @@ config SOC_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select NO_MONOTONIC_TIMER
select NO_MMCONF_SUPPORT
select NO_ECAM_MMCONF_SUPPORT
select UNKNOWN_TSC_RATE
config DCACHE_BSP_STACK_SIZE # required by arch/x86/car.ld

2
src/soc/intel/alderlake/Kconfig
View File

@ -203,7 +203,7 @@ config PCR_BASE_ADDRESS
help
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xc0000000
config CPU_BCLK_MHZ

2
src/soc/intel/alderlake/systemagent.c
View File

@ -25,7 +25,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/apollolake/systemagent.c
View File

@ -18,7 +18,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
};

4
src/soc/intel/baytrail/Kconfig
View File

@ -39,10 +39,10 @@ config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 256

8
src/soc/intel/baytrail/acpi/southcluster.asl
View File

@ -144,7 +144,7 @@ Name (MCRS, ResourceTemplate()
0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000,,, LMEM)
/* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */
/* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@ -184,7 +184,7 @@ Method (_CRS, 0, Serialized)
/* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
Store (\TOLM, PMIN)
Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
Store (Subtract(CONFIG_ECAM_MMCONF_BASE_ADDRESS, 1), PMAX)
Add (Subtract (PMAX, PMIN), 1, PLEN)
Return (MCRS)
@ -198,7 +198,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
@ -247,7 +247,7 @@ Device (IOSF)
Method (_CRS)
{
CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
Return (^RBUF)
}
}

2
src/soc/intel/baytrail/bootblock/bootblock.c
View File

@ -89,7 +89,7 @@ static void setup_mmconfig(void)
reg = 0;
/* Clear the extended register. */
pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | 1;
pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;

4
src/soc/intel/braswell/Kconfig
View File

@ -54,10 +54,10 @@ config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 256

8
src/soc/intel/braswell/acpi/southcluster.asl
View File

@ -146,7 +146,7 @@ Method (_CRS, 0, Serialized)
0x00000000, 0x20000000, 0x201FFFFF, 0x00000000,
0x00200000,,, LMEM)
/* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */
/* PCI Memory Region (Top of memory-CONFIG_ECAM_MMCONF_BASE_ADDRESS) */
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite,
0x00000000, 0x00000000, 0x00000000, 0x00000000,
@ -183,7 +183,7 @@ Method (_CRS, 0, Serialized)
/* TOLM is BMBOUND accessible from IOSF so is saved in NVS */
Store (\TOLM, PMIN)
Store (Subtract(CONFIG_MMCONF_BASE_ADDRESS, 1), PMAX)
Store (Subtract(CONFIG_ECAM_MMCONF_BASE_ADDRESS, 1), PMAX)
Add (Subtract (PMAX, PMIN), 1, PLEN)
Return (MCRS)
@ -197,7 +197,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE)
Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE)
Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE)
Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE)
@ -246,7 +246,7 @@ Device (IOSF)
Method (_CRS)
{
CreateDwordField (^RBUF, ^RBAR._BAS, RBAS)
Store (Add (CONFIG_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
Store (Add (CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0xD0), RBAS)
Return (^RBUF)
}
}

2
src/soc/intel/braswell/bootblock/bootblock.c
View File

@ -100,7 +100,7 @@ static void setup_mmconfig(void)
reg = 0;
/* Clear the extended register. */
pci_io_write_config32(IOSF_PCI_DEV, MCRX_REG, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 1;
reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | 1;
pci_io_write_config32(IOSF_PCI_DEV, MDR_REG, reg);
reg = IOSF_OPCODE(IOSF_OP_WRITE_BUNIT) | IOSF_PORT(IOSF_PORT_BUNIT) |
IOSF_REG(BUNIT_MMCONF_REG) | IOSF_BYTE_EN;

4
src/soc/intel/broadwell/Kconfig
View File

@ -33,10 +33,10 @@ config VBOOT
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_ROMSTAGE if !BROADWELL_VBOOT_IN_BOOTBLOCK
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xf0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 64
config VGA_BIOS_ID

8
src/soc/intel/broadwell/bootblock.c
View File

@ -8,7 +8,7 @@
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
@ -20,15 +20,15 @@ void bootblock_early_northbridge_init(void)
{
/*
* The "io" variant of the config access is explicitly used to setup the
* PCIEXBAR because CONFIG(MMCONF_SUPPORT) is set to true. That way, all
* PCIEXBAR because CONFIG(ECAM_MMCONF_SUPPORT) is set to true. That way, all
* subsequent non-explicit config accesses use MCFG. This code also assumes
* that bootblock_northbridge_init() is the first thing called in the non-asm
* boot block code. The final assumption is that no assembly code is using the
* CONFIG(MMCONF_SUPPORT) option to do PCI config accesses.
* CONFIG(ECAM_MMCONF_SUPPORT) option to do PCI config accesses.
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
const uint32_t reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR + 4, 0);
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
}

2
src/soc/intel/broadwell/pei_data.c
View File

@ -15,7 +15,7 @@ void broadwell_fill_pei_data(struct pei_data *pei_data)
pei_data->pei_version = PEI_VERSION;
pei_data->board_type = BOARD_TYPE_ULT;
pei_data->usbdebug = CONFIG(USBDEBUG);
pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS;
pei_data->pciexbar = CONFIG_ECAM_MMCONF_BASE_ADDRESS;
pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
pei_data->ehcibar = CONFIG_EHCI_BAR;
pei_data->xhcibar = 0xd7000000;

2
src/soc/intel/cannonlake/systemagent.c
View File

@ -20,7 +20,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

4
src/soc/intel/common/block/systemagent/Kconfig
View File

@ -5,10 +5,10 @@ config SOC_INTEL_COMMON_BLOCK_SA
if SOC_INTEL_COMMON_BLOCK_SA
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 256
config SA_ENABLE_IMR

4
src/soc/intel/common/block/systemagent/systemagent_early.c
View File

@ -29,7 +29,7 @@ void bootblock_systemagent_early_init(void)
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR + 4, reg);
/* Get PCI Express Region Length */
switch (CONFIG_MMCONF_BUS_NUMBER) {
switch (CONFIG_ECAM_MMCONF_BUS_NUMBER) {
case 256:
pciexbar_length = PCIEXBAR_LENGTH_256MB;
break;
@ -42,7 +42,7 @@ void bootblock_systemagent_early_init(void)
default:
dead_code();
}
reg = CONFIG_MMCONF_BASE_ADDRESS | (pciexbar_length << 1)
reg = CONFIG_ECAM_MMCONF_BASE_ADDRESS | (pciexbar_length << 1)
| PCIEXBAR_PCIEXBAREN;
pci_io_write_config32(SA_DEV_ROOT, PCIEXBAR, reg);

4
src/soc/intel/denverton_ns/Kconfig
View File

@ -44,10 +44,10 @@ config CPU_SPECIFIC_OPTIONS
select FSP_T_XIP if FSP_CAR
select FSP_M_XIP
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xe0000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
int
default 256

2
src/soc/intel/denverton_ns/acpi/northcluster.asl
View File

@ -122,7 +122,7 @@ Device (PDRC)
Name (PDRS, ResourceTemplate() {
// PCIEXBAR memory range
Memory32Fixed(ReadOnly, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH)
Memory32Fixed(ReadOnly, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH)
// TSEG
Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, TSMB)
})

4
src/soc/intel/denverton_ns/bootblock/bootblock.c
View File

@ -74,8 +74,8 @@ static void sanity_check_pci_mmconf(void)
break;
}
assert(base == CONFIG_MMCONF_BASE_ADDRESS);
assert(length == CONFIG_MMCONF_BUS_NUMBER);
assert(base == CONFIG_ECAM_MMCONF_BASE_ADDRESS);
assert(length == CONFIG_ECAM_MMCONF_BUS_NUMBER);
}
void bootblock_soc_early_init(void)

2
src/soc/intel/elkhartlake/Kconfig
View File

@ -130,7 +130,7 @@ config PCR_BASE_ADDRESS
help
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xc0000000
config CPU_BCLK_MHZ

2
src/soc/intel/elkhartlake/systemagent.c
View File

@ -19,7 +19,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/icelake/Kconfig
View File

@ -118,7 +118,7 @@ config PCR_BASE_ADDRESS
help
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xc0000000
config CPU_BCLK_MHZ

2
src/soc/intel/icelake/systemagent.c
View File

@ -15,7 +15,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/jasperlake/Kconfig
View File

@ -126,7 +126,7 @@ config PCR_BASE_ADDRESS
help
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xc0000000
config CPU_BCLK_MHZ

2
src/soc/intel/jasperlake/systemagent.c
View File

@ -19,7 +19,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/quark/Kconfig
View File

@ -10,7 +10,7 @@ if SOC_INTEL_QUARK
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select NO_MMCONF_SUPPORT
select NO_ECAM_MMCONF_SUPPORT
select REG_SCRIPT
select PLATFORM_USES_FSP2_0
select SOC_INTEL_COMMON

2
src/soc/intel/skylake/systemagent.c
View File

@ -34,7 +34,7 @@ bool soc_vtd_enabled(void)
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

2
src/soc/intel/tigerlake/Kconfig
View File

@ -161,7 +161,7 @@ config PCR_BASE_ADDRESS
help
This option allows you to select MMIO Base Address of sideband bus.
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0xc0000000
config CPU_BCLK_MHZ

2
src/soc/intel/tigerlake/systemagent.c
View File

@ -27,7 +27,7 @@
void soc_add_fixed_mmio_resources(struct device *dev, int *index)
{
static const struct sa_mmio_descriptor soc_fixed_resources[] = {
{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH,
{ PCIEXBAR, CONFIG_ECAM_MMCONF_BASE_ADDRESS, CONFIG_ECAM_MMCONF_LENGTH,
"PCIEXBAR" },
{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },

4
src/soc/intel/xeon_sp/Kconfig
View File

@ -103,10 +103,10 @@ config DCACHE_BSP_STACK_SIZE
hex
default 0x10000
config MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BASE_ADDRESS
default 0x80000000
config MMCONF_BUS_NUMBER
config ECAM_MMCONF_BUS_NUMBER
default 256
config HEAP_SIZE

2
src/soc/intel/xeon_sp/uncore.c
View File

@ -137,7 +137,7 @@ static void configure_dpr(struct device *dev)
* | P2SB PCR cfg BAR | (0xfd000000 - 0xfdffffff
* | BAR space | [mem 0x90000000-0xfcffffff] available for PCI devices
* +--------------------------+ 0x9000_0000
* |PCIe MMCFG (relocatable) | CONFIG_MMCONF_BASE_ADDRESS 64 or 256MB
* |PCIe MMCFG (relocatable) | CONFIG_ECAM_MMCONF_BASE_ADDRESS 64 or 256MB
* | | (0x80000000 - 0x8fffffff, 0x40000)
* +--------------------------+ TOLM
* | MEseg (relocatable) | 32, 64, 128 or 256 MB (0x78000000 - 0x7fffffff, 0x20000)

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