northbridge/amd/amdfam10: Add Suspend to RAM (S3) Flash data storage area
Change-Id: I169fafc3a61e11c3e4781190053e57bf34502d7b Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11951 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -93,6 +93,16 @@ if DIMM_FBDIMM
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default 0x0110
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endif
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config S3_DATA_SIZE
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int
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default 16384
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depends on (HAVE_ACPI_RESUME)
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config S3_DATA_POS
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int
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default 0
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depends on (HAVE_ACPI_RESUME)
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if DIMM_DDR2
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if DIMM_REGISTERED
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config DIMM_SUPPORT
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@ -15,4 +15,17 @@ ramstage-y += get_pci1234.c
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# Call show_all_routes() anywhere amdfam10.h is included.
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#ramstage-y += util.c
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# Reserve 2x CONFIG_S3_DATA_SIZE to allow for random file placement
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# (not respecting erase sector boundaries) within CBFS
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$(obj)/coreboot_s3nv.rom: $(obj)/config.h
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echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)"
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# force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse)
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printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1*2; i++) {printf "%c", 255}}' > $@.tmp
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mv $@.tmp $@
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cbfs-files-$(CONFIG_HAVE_ACPI_RESUME) += s3nv
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s3nv-file := $(obj)/coreboot_s3nv.rom
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s3nv-align := $(CONFIG_S3_DATA_SIZE)
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s3nv-type := raw
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endif
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@ -108,6 +108,10 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t registered, uint16_t freq
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#include "../amdmct/mct_ddr3/mct_d.h"
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#include "../amdmct/mct_ddr3/mct_d_gcc.h"
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#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
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#include "../amdmct/mct_ddr3/s3utils.c"
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#endif
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#include "../amdmct/wrappers/mcti_d.c"
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#include "../amdmct/mct_ddr3/mct_d.c"
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@ -246,32 +250,34 @@ static void amdmct_cbmem_store_info(struct sys_info *sysinfo)
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size_t i;
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struct DCTStatStruc *pDCTstatA = NULL;
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/* Allocate memory */
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struct amdmct_memory_info* mem_info;
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mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info));
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if (!mem_info)
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return;
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if (!acpi_is_wakeup_s3()) {
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/* Allocate memory */
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struct amdmct_memory_info *mem_info;
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mem_info = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, sizeof(struct amdmct_memory_info));
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if (!mem_info)
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return;
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printk(BIOS_DEBUG, "%s: Storing AMDMCT configuration in CBMEM\n", __func__);
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printk(BIOS_DEBUG, "%s: Storing AMDMCT configuration in CBMEM\n", __func__);
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/* Initialize memory */
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memset(mem_info, 0, sizeof(struct amdmct_memory_info));
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/* Initialize memory */
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memset(mem_info, 0, sizeof(struct amdmct_memory_info));
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/* Copy data */
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memcpy(&mem_info->mct_stat, &(sysinfo->MCTstat), sizeof(struct MCTStatStruc));
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for (i = 0; i < MAX_NODES_SUPPORTED; i++) {
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pDCTstatA = sysinfo->DCTstatA + i;
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memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc));
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}
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mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP);
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mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub);
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/* Copy data */
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memcpy(&mem_info->mct_stat, &sysinfo->MCTstat, sizeof(struct MCTStatStruc));
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for (i = 0; i < MAX_NODES_SUPPORTED; i++) {
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pDCTstatA = sysinfo->DCTstatA + i;
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memcpy(&mem_info->dct_stat[i], pDCTstatA, sizeof(struct DCTStatStruc));
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}
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mem_info->ecc_enabled = mctGet_NVbits(NV_ECC_CAP);
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mem_info->ecc_scrub_rate = mctGet_NVbits(NV_DramBKScrub);
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/* Zero out invalid/unused pointers */
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/* Zero out invalid/unused pointers */
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#if IS_ENABLED(CONFIG_DIMM_DDR3)
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for (i = 0; i < MAX_NODES_SUPPORTED; i++) {
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mem_info->dct_stat[i].C_MCTPtr = NULL;
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mem_info->dct_stat[i].C_DCTPtr[0] = NULL;
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mem_info->dct_stat[i].C_DCTPtr[1] = NULL;
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}
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for (i = 0; i < MAX_NODES_SUPPORTED; i++) {
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mem_info->dct_stat[i].C_MCTPtr = NULL;
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mem_info->dct_stat[i].C_DCTPtr[0] = NULL;
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mem_info->dct_stat[i].C_DCTPtr[1] = NULL;
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}
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#endif
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}
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}
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