diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index 78da91fc3e..db244b9964 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -88,6 +88,17 @@ chip soc/intel/alderlake
 		[PchSerialIoIndexI2C5] = PchSerialIoPci,
 	}"
 
+	# SOC Aux orientation override:
+	# This is a bitfield that corresponds to up to 4 TCSS ports.
+	# Bits (0,1) are allocated for TCSS Port1 configuration and Bits (2,3) for TCSS Port2.
+	# TcssAuxOri = 0101b
+	# Bit0, Bit2 set to "1" indicates no retimer on USB-C Ports
+	# Bit1, Bit3 set to "0" indicates Aux lines are not swapped on the
+	# motherboard to USB-C connector
+	register "tcss_aux_ori" = "1"
+	register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22,
+                                              .pad_auxn_dc = GPP_E23}"
+
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# USB2_C0
 	register "usb2_ports[1]" = "USB2_PORT_EMPTY"		# Disable USB2_Port 1
 	register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC1)"	# USB2_C2
@@ -104,9 +115,7 @@ chip soc/intel/alderlake
 	register "usb3_ports[2]" = "USB3_PORT_EMPTY"		# Disable USB3 Port 2
 	register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC2)"	# USB3/2 Type A port A1
 
-	register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)"
 	register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
-	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC1)"
 
 	register "tcc_offset" = "5"     # TCC of 100