mb/asus/p2b*: Switch to overridetree
All variants will use the same lid/thermal-polarity config as a result, which looks the same for all recently boot-tested variants anyway. Change-Id: Iaaae4eae41ab0037e72375b255d9d1c3eca8d383 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39905 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -56,9 +56,9 @@ config VARIANT_DIR
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default "p2b-f" if BOARD_ASUS_P2B_F
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default "p2b-ls" if BOARD_ASUS_P2B_LS
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config DEVICETREE
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config OVERRIDE_DEVICETREE
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string
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default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" if ! BOARD_ASUS_P2B
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default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
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config IRQ_SLOT_COUNT
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int
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@ -37,10 +37,6 @@ chip northbridge/intel/i440bx # Northbridge
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end
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device pnp 3f0.8 on # GPIO 2
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end
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device pnp 3f0.9 on # GPIO 3
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end
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device pnp 3f0.a on # ACPI
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end
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end
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end
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device pci 4.1 on end # IDE
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@ -56,7 +52,6 @@ chip northbridge/intel/i440bx # Northbridge
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register "ide1_drive1_udma33_enable" = "0"
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register "thrm_polarity" = "1"
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register "lid_polarity" = "1"
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register "gpo" = "0x7fffbbff"
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end
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end
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end
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@ -8,47 +8,15 @@ chip northbridge/intel/i440bx # Northbridge
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end
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end
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device domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 3f0.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.3 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.5 on # PS/2 keyboard / mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.7 on # GPIO 1
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end
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device pnp 3f0.8 on # GPIO 2
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end
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device pnp 3f0.9 on # GPIO 3
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end
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device pnp 3f0.a on # ACPI
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end
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end
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end
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device pci 4.1 on end # IDE
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device pci 4.2 on end # USB
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device pci 4.3 on end # ACPI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "ide_legacy_enable" = "1"
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@ -8,47 +8,15 @@ chip northbridge/intel/i440bx # Northbridge
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end
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end
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device domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 3f0.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.3 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.5 on # PS/2 keyboard / mouse
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.7 on # GPIO 1
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end
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device pnp 3f0.8 on # GPIO 2
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end
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device pnp 3f0.9 on # GPIO 3
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end
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device pnp 3f0.a on # ACPI
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end
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end
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end
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device pci 4.1 on end # IDE
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device pci 4.2 on end # USB
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device pci 4.3 on end # ACPI
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device pci 6.0 on end # Onboard SCSI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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@ -1,59 +0,0 @@
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chip northbridge/intel/i440bx # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device lapic 0 on end # APIC
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end
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end
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device domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 3f0.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.3 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.6 on # Consumer IR
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end
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device pnp 3f0.7 on # GPIO 1
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end
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device pnp 3f0.8 on # GPIO 2
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end
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device pnp 3f0.a on # ACPI
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end
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end
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end
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device pci 4.1 on end # IDE
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device pci 4.2 on end # USB
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device pci 4.3 on end # ACPI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "ide_legacy_enable" = "1"
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# Enable UDMA/33 for higher speed if your IDE device(s) support it.
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register "ide0_drive0_udma33_enable" = "0"
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register "ide0_drive1_udma33_enable" = "0"
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register "ide1_drive0_udma33_enable" = "0"
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register "ide1_drive1_udma33_enable" = "0"
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end
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end
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end
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@ -0,0 +1,14 @@
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chip northbridge/intel/i440bx # Northbridge
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device domain 0 on # PCI domain
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chip southbridge/intel/i82371eb # Southbridge
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
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device pnp 3f0.6 on # Consumer IR
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end
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device pnp 3f0.a on # ACPI
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end
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end
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end
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end
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end
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end
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@ -1,58 +0,0 @@
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chip northbridge/intel/i440bx # Northbridge
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device cpu_cluster 0 on # APIC cluster
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chip cpu/intel/slot_1 # CPU
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device lapic 0 on end # APIC
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end
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end
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device domain 0 on # PCI domain
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device pci 0.0 on end # Host bridge
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device pci 1.0 on end # PCI/AGP bridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O (FIXME: It's W83977EF!)
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device pnp 3f0.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.1 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 3f0.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 3f0.3 on # COM2 / IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 3f0.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1 # PS/2 keyboard interrupt
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.7 on # GPIO 1
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end
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device pnp 3f0.8 on # GPIO 2
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end
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device pnp 3f0.a off # ACPI
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end
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end
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end
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device pci 4.1 on end # IDE
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device pci 4.2 on end # USB
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device pci 4.3 on end # ACPI
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device pci 6.0 on end # Onboard SCSI
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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register "ide_legacy_enable" = "1"
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# Enable UDMA/33 for higher speed if your IDE device(s) support it.
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register "ide0_drive0_udma33_enable" = "0"
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register "ide0_drive1_udma33_enable" = "0"
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register "ide1_drive0_udma33_enable" = "0"
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register "ide1_drive1_udma33_enable" = "0"
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end
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end
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end
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@ -0,0 +1,12 @@
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chip northbridge/intel/i440bx # Northbridge
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device domain 0 on # PCI domain
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chip southbridge/intel/i82371eb # Southbridge
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O
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device pnp 3f0.a off # ACPI
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end
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end
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end
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end
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end
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end
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@ -0,0 +1,15 @@
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chip northbridge/intel/i440bx # Northbridge
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device domain 0 on # PCI domain
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chip southbridge/intel/i82371eb # Southbridge
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register "gpo" = "0x7fffbbff"
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device pci 4.0 on # ISA bridge
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chip superio/winbond/w83977tf # Super I/O
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device pnp 3f0.9 on # GPIO 3
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end
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device pnp 3f0.a on # ACPI
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end
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end
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end
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end
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end
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end
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