rockchip/rk3399: set edp pclk to 25MHz
It may cause an edp aux transfer error if the edp pclk is set too high, so reduce it to 25MHz. BUG=chrome-os-partner:60130 BRANCH=None TEST=Build and Boot Change-Id: Id1063baa5a82637b03c0f1f754181df074ab17cc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 8f7ce31a7483e765ae0c86f8e62ef51413ee1596 Original-Change-Id: Ibb86c12c1d7c00dc3b4cc7a6bdf3bd6e895cd9f3 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/429410 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -181,6 +181,13 @@ enum {
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CLK_TSADC_DIV_CON_MASK = 0x3ff,
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CLK_TSADC_DIV_CON_SHIFT = 0,
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/* CLKSEL_CON44 */
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CLK_PCLK_EDP_PLL_SEL_MASK = 1,
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CLK_PCLK_EDP_PLL_SEL_SHIFT = 15,
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CLK_PCLK_EDP_PLL_SEL_CPLL = 0,
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CLK_PCLK_EDP_DIV_CON_MASK = 0x3f,
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CLK_PCLK_EDP_DIV_CON_SHIFT = 8,
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/* CLKSEL_CON47 & CLKSEL_CON48 */
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ACLK_VOP_PLL_SEL_MASK = 0x3,
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ACLK_VOP_PLL_SEL_SHIFT = 6,
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@ -838,3 +845,21 @@ int rkclk_was_watchdog_reset(void)
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/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
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return read32(&cru_ptr->glb_rst_st) & 0x30;
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}
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void rkclk_configure_edp(unsigned int hz)
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{
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int src_clk_div;
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src_clk_div = CPLL_HZ / hz;
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assert((src_clk_div - 1 <= 63) && (src_clk_div * hz == CPLL_HZ));
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write32(&cru_ptr->clksel_con[44],
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RK_CLRSETBITS(CLK_PCLK_EDP_PLL_SEL_MASK <<
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CLK_PCLK_EDP_PLL_SEL_SHIFT |
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CLK_PCLK_EDP_DIV_CON_MASK <<
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CLK_PCLK_EDP_DIV_CON_SHIFT,
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CLK_PCLK_EDP_PLL_SEL_CPLL <<
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CLK_PCLK_EDP_PLL_SEL_SHIFT |
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(src_clk_div - 1) <<
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CLK_PCLK_EDP_DIV_CON_SHIFT));
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}
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@ -65,6 +65,7 @@ void rk_display_init(device_t dev)
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case VOP_MODE_EDP:
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printk(BIOS_DEBUG, "Attempting to set up EDP display.\n");
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rkclk_configure_vop_aclk(vop_id, 200 * MHz);
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rkclk_configure_edp(25 * MHz);
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/* select edp signal from vop0 */
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write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5));
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@ -119,5 +119,6 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz);
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void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy);
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int rkclk_was_watchdog_reset(void);
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uint32_t rkclk_i2c_clock_for_bus(unsigned bus);
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void rkclk_configure_edp(unsigned int hz);
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#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */
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