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soc/intel: Use of common reset code block 

This patch removes all redundant reset code block from each SoC
and make use of common reset code block(fsp_reset.c) based on
SOC_INTEL_COMMON_FSP_RESET.

Respective SoC Kconfig to choose correct FSP global reset type as
per FSP integration guide.

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2020-10-31 22:01:55 +05:30 committed by Patrick Georgi
parent 2b2ade9638
commit 4ed9f9a507
16 changed files with 16 additions and 132 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/alderlake/Kconfig
View File

@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_SUPPORTS_PM_TIMER_EMULATION select CPU_SUPPORTS_PM_TIMER_EMULATION
select FSP_COMPRESS_FSP_S_LZ4 select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAVE_FSP_GOP select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
@ -49,6 +50,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CAR

17
src/soc/intel/alderlake/reset.c
View File

@ -1,12 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <fsp/util.h>
#include <soc/intel/common/reset.h> #include <soc/intel/common/reset.h>
#include <soc/pci_devs.h>
void do_global_reset(void) void do_global_reset(void)
{ {
@ -18,17 +15,3 @@ void do_global_reset(void)
pmc_global_reset_enable(1); pmc_global_reset_enable(1);
do_full_reset(); do_full_reset();
} }
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
die("unknown reset type");
break;
}
}

2
src/soc/intel/apollolake/Kconfig
View File

@ -38,6 +38,7 @@ config CPU_SPECIFIC_OPTIONS
# Misc options # Misc options
select CACHE_MRC_SETTINGS select CACHE_MRC_SETTINGS
select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS
select FSP_STATUS_GLOBAL_RESET_REQUIRED_5
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
@ -91,6 +92,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_SPI
select SOC_INTEL_COMMON_BLOCK_CSE select SOC_INTEL_COMMON_BLOCK_CSE
select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SMBUS
select SOC_INTEL_COMMON_FSP_RESET
select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select UDELAY_TSC select UDELAY_TSC
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER

14
src/soc/intel/apollolake/reset.c
View File

@ -3,7 +3,6 @@
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h> #include <console/console.h>
#include <delay.h> #include <delay.h>
#include <fsp/util.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <soc/heci.h> #include <soc/heci.h>
#include <soc/intel/common/reset.h> #include <soc/intel/common/reset.h>
@ -47,16 +46,3 @@ void cf9_reset_prepare(void)
} }
printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw)); printk(BIOS_SPEW, "CSE took %lu ms\n", stopwatch_duration_msecs(&sw));
} }
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_5: /* Global Reset */
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
die("unknown reset type");
break;
}
}

2
src/soc/intel/cannonlake/Kconfig
View File

@ -82,6 +82,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_SUPPORTS_PM_TIMER_EMULATION select CPU_SUPPORTS_PM_TIMER_EMULATION
select FSP_COMPRESS_FSP_S_LZMA select FSP_COMPRESS_FSP_S_LZMA
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAVE_FSP_GOP select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT select HAVE_FSP_LOGO_SUPPORT
@ -120,6 +121,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_COMMON_FSP_RESET
select SSE2 select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
select TSC_MONOTONIC_TIMER select TSC_MONOTONIC_TIMER

17
src/soc/intel/cannonlake/reset.c
View File

@ -1,12 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <fsp/util.h>
#include <soc/intel/common/reset.h> #include <soc/intel/common/reset.h>
#include <soc/pci_devs.h>
void do_global_reset(void) void do_global_reset(void)
{ {
@ -18,17 +15,3 @@ void do_global_reset(void)
pmc_global_reset_enable(1); pmc_global_reset_enable(1);
do_full_reset(); do_full_reset();
} }
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
die("unknown reset type");
break;
}
}

2
src/soc/intel/elkhartlake/Kconfig
View File

@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_SUPPORTS_PM_TIMER_EMULATION select CPU_SUPPORTS_PM_TIMER_EMULATION
select FSP_COMPRESS_FSP_S_LZ4 select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAVE_FSP_GOP select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
@ -50,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CAR

17
src/soc/intel/elkhartlake/reset.c
View File

@ -1,12 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <soc/intel/common/reset.h> #include <soc/intel/common/reset.h>
#include <soc/pci_devs.h>
void do_global_reset(void) void do_global_reset(void)
{ {
@ -18,17 +15,3 @@ void do_global_reset(void)
pmc_global_reset_enable(1); pmc_global_reset_enable(1);
do_full_reset(); do_full_reset();
} }
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
die("unknown reset type");
break;
}
}

2
src/soc/intel/icelake/Kconfig
View File

@ -16,6 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION select CPU_SUPPORTS_PM_TIMER_EMULATION
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAVE_FSP_GOP select HAVE_FSP_GOP
select HAVE_INTEL_FSP_REPO select HAVE_INTEL_FSP_REPO
@ -51,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_BLOCK_THERMAL select SOC_INTEL_COMMON_BLOCK_THERMAL
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CAR

17
src/soc/intel/icelake/reset.c
View File

@ -1,12 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <fsp/util.h>
#include <soc/intel/common/reset.h> #include <soc/intel/common/reset.h>
#include <soc/pci_devs.h>
void do_global_reset(void) void do_global_reset(void)
{ {
@ -18,17 +15,3 @@ void do_global_reset(void)
pmc_global_reset_enable(1); pmc_global_reset_enable(1);
do_full_reset(); do_full_reset();
} }
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
die("unknown reset type");
break;
}
}

2
src/soc/intel/jasperlake/Kconfig
View File

@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS
select COS_MAPPED_TO_MSB select COS_MAPPED_TO_MSB
select FSP_COMPRESS_FSP_S_LZ4 select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAVE_FSP_GOP select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
@ -50,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CAR

17
src/soc/intel/jasperlake/reset.c
View File

@ -1,12 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <fsp/util.h>
#include <soc/intel/common/reset.h> #include <soc/intel/common/reset.h>
#include <soc/pci_devs.h>
void do_global_reset(void) void do_global_reset(void)
{ {
@ -18,17 +15,3 @@ void do_global_reset(void)
pmc_global_reset_enable(1); pmc_global_reset_enable(1);
do_full_reset(); do_full_reset();
} }
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
die("unknown reset type");
break;
}
}

2
src/soc/intel/skylake/Kconfig
View File

@ -26,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_SUPPORTS_PM_TIMER_EMULATION select CPU_SUPPORTS_PM_TIMER_EMULATION
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAVE_FSP_GOP select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT select HAVE_FSP_LOGO_SUPPORT
@ -63,6 +64,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_THERMAL select SOC_INTEL_COMMON_BLOCK_THERMAL
select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_UART
select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET

16
src/soc/intel/skylake/reset.c
View File

@ -1,8 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h>
#include <fsp/util.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <soc/intel/common/reset.h> #include <soc/intel/common/reset.h>
#include <soc/me.h> #include <soc/me.h>
@ -30,17 +28,3 @@ void do_global_reset(void)
do_force_global_reset(); do_force_global_reset();
} }
} }
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
die("unknown reset type");
break;
}
}

2
src/soc/intel/tigerlake/Kconfig
View File

@ -17,6 +17,7 @@ config CPU_SPECIFIC_OPTIONS
select DRIVERS_USB_ACPI select DRIVERS_USB_ACPI
select FSP_COMPRESS_FSP_S_LZ4 select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAVE_FSP_GOP select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
@ -53,6 +54,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4
select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_PCIE
select SOC_INTEL_COMMON_BLOCK_USB4_XHCI select SOC_INTEL_COMMON_BLOCK_USB4_XHCI
select SOC_INTEL_COMMON_FSP_RESET
select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CAR

17
src/soc/intel/tigerlake/reset.c
View File

@ -1,12 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <cf9_reset.h> #include <cf9_reset.h>
#include <console/console.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <fsp/util.h>
#include <soc/intel/common/reset.h> #include <soc/intel/common/reset.h>
#include <soc/pci_devs.h>
void do_global_reset(void) void do_global_reset(void)
{ {
@ -18,17 +15,3 @@ void do_global_reset(void)
pmc_global_reset_enable(1); pmc_global_reset_enable(1);
do_full_reset(); do_full_reset();
} }
void chipset_handle_reset(uint32_t status)
{
switch (status) {
case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */
printk(BIOS_DEBUG, "GLOBAL RESET!!\n");
global_reset();
break;
default:
printk(BIOS_ERR, "unhandled reset type %x\n", status);
die("unknown reset type");
break;
}
}