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Move AMD SB800 early clock setup. 

Move the AMD SB800 early clock setup code that is needed for early
serial port operation from mainboard/romstage.c to sb800/bootblock.c.
This prevents code duplication and simplifies porting.

Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/96
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Scott Duplichan 2011-07-13 17:34:16 -06:00 committed by Peter Stuge
parent 9229af963d
commit 4edbe004b8
3 changed files with 21 additions and 30 deletions
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15
src/mainboard/amd/persimmon/romstage.c
View File

@ -55,21 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr (0xc0010062, 0);
if (boot_cpu())
{
u8 reg8;
// SB800: program AcpiMmioEn to enable MMIO access to MiscCntrl register
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
outb(reg8, 0xCD7);
// program SB800 MiscCntrl
*(volatile u32 *)(0xFED80000+0xE00+0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000+0xE00+0x40) |= 1 << 1; /* 48Mhz */
}
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_poweron_init();

15
src/mainboard/asrock/e350m1/romstage.c
View File

@ -55,21 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
__writemsr(0xc0010062, 0);
if (boot_cpu()) {
u8 reg8;
// SB800: Program AcpiMmioEn to enable MMIO access to MiscCntrl register
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
outb(0x24, 0xCD6);
outb(reg8, 0xCD7);
// Program SB800 MiscCntrl
*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(0xFED80000 + 0xE00 + 0x40) |= 1 << 1; /* 48Mhz */
}
if (!cpu_init_detectedx && boot_cpu()) {
post_code(0x30);
sb_poweron_init();

21
src/southbridge/amd/cimx/sb800/bootblock.c
View File

@ -84,10 +84,31 @@ static void enable_spi_fast_mode(void)
pci_io_write_config32(dev, 0xa0, save);
}
static void enable_clocks(void)
{
u8 reg8;
u32 reg32;
volatile u32 *acpi_mmio = (void *) (0xFED80000 + 0xE00 + 0x40);
// Program AcpiMmioEn to enable MMIO access to MiscCntrl register
outb(0x24, 0xCD6);
reg8 = inb(0xCD7);
reg8 |= 1;
reg8 &= ~(1 << 1);
outb(reg8, 0xCD7);
// Program SB800 MiscCntrl Device_CLK1_sel for 48 MHz (default is 14 MHz)
reg32 = *acpi_mmio;
reg32 &= ~((1 << 0) | (1 << 2));
reg32 |= 1 << 1;
*acpi_mmio = reg32;
}
static void bootblock_southbridge_init(void)
{
/* Setup the rom access for 2M */
enable_rom();
enable_prefetch();
enable_spi_fast_mode();
enable_clocks();
}