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soc/intel/alderlake: Reduce memory test size 

Enable upd to reduce size of the memory test.

BUG=b:268546941
TEST=Observe boot time improvement with these two UPDs set

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I95c7d8503596c2712d7abe123ed1f911ac4abacf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Bora Guvendik 2023-04-24 17:13:58 -07:00 committed by Nick Vaccaro
parent 433343eaaa
commit 4ee03dc445
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/alderlake/chipset.cb
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@ -90,6 +90,9 @@ chip soc/intel/alderlake
.tdp_pl4 = 114, .tdp_pl4 = 114,
}" }"
# Reduce the size of BasicMemoryTests to speed up the boot time.
register "lower_basic_mem_test_size" = "true"
# NOTE: if any variant wants to override this value, use the same format # NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of # as register "common_soc_config.pch_thermal_trip" = "value", instead of
# putting it under register "common_soc_config" in overridetree.cb file. # putting it under register "common_soc_config" in overridetree.cb file.