Documentation/Intel: More CorebootPayloadPkg documentation
Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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Lee Leahy
Leroy P Leahy
parent
ca20b5fa6f
commit
4ee073d476
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@ -47,7 +47,7 @@
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<hr>
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<h1>Quark™ EDK2 CorebootPayloadPkg</h1>
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<h1><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h1>
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<p>
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Build Instructions:
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</p>
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@ -214,6 +214,6 @@ Documentation:
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<hr>
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<p>Modified: 20 February 2016</p>
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<p>Modified: 24 February 2016</p>
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</body>
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</html>
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@ -33,6 +33,7 @@
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</ol>
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</li>
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<li><a href="#AcpiTables">ACPI Tables</a></li>
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<li><a href="#LegacyHardware">Legacy Hardware</a></li>
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</ol>
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@ -560,7 +561,7 @@ Use the following steps to debug the call to TempRamInit:
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<hr>
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<h1><a name="AcpiTables">ACPI Tables</a></h1>
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<p>
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One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg.
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One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.
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</p>
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<h2>FADT</h2>
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@ -664,6 +665,57 @@ Use the following steps to debug the call to TempRamInit:
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</ol>
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<hr>
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<h1><a name="LegacyHardware">Legacy Hardware</a></h1>
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<p>
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One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>.
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</p>
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<table border="1">
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<tr bgcolor="c0ffc0">
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<th>Peripheral</th>
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<th>Use</th>
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<th>8259 Interrupt Vector</th>
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<th>IDT Base Offset</th>
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<th>Interrupt Handler</th>
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</tr>
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<tr>
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<td>
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<a target="_blank" href="http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf">8254</a>
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Programmable Interval Timer
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</td>
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<td>
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EDK2: PcAtChipsetPkg/8254TimerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c">Timer.c</a>
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</td>
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<td>0</td>
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<td>0x340</td>
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<td>
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<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/Timer.c#l71">TimerInterruptHandler</a>
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</td>
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</tr>
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<tr>
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<td>
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<a target="_blank" href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uact=8&ved=0ahUKEwibxYKU3ZDLAhVOzWMKHfuqB40QFggcMAA&url=http%3A%2F%2Fbochs.sourceforge.net%2Ftechspec%2Fintel-8259a-pic.pdf.gz&usg=AFQjCNF1NT0OQ6ys1Pn6Iv9sv6cKRzZbGg&sig2=HfBszp9xTVO_fajjPWCsJw">8259</a>
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Programmable Interrupt Controller
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</td>
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<td>
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EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptControllerDxe/8259.c">8259.c</a>
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</td>
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<td>
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Master interrupts: 0, 2 - 7<br>
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Slave interrupts: 8 - 15<br>
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Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15
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</td>
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<td>
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Master: 0x340, 0x350 - 0x378<br>
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Slave: 0x380 - 0x3b8<br>
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Interrupt descriptors are 8 bytes each
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</td>
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<td> </td>
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</tr>
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</table>
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<hr>
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<p>Modified: 28 February 2016</p>
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</body>
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@ -125,6 +125,7 @@
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<li>Payload and OS Features:
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<ul>
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<li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li>
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<li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li>
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</ul>
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</li>
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</ul>
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@ -141,6 +142,16 @@
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<th>Where</th>
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<th>Testing</th>
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</tr>
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<tr>
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<td>8254 Programmable Interval Timer</td>
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<td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
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<td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
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</tr>
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<tr>
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<td>8259 Programmable Interrupt Controller</td>
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<td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td>
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<td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td>
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</tr>
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<tr>
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<td>Cache-as-RAM</td>
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<td>
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@ -335,6 +346,6 @@
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<hr>
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<p>Modified: 20 February 2016</p>
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<p>Modified: 24 February 2016</p>
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</body>
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</html>
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@ -21,6 +21,7 @@
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<h1>x86 coreboot Development</h1>
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<ul>
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<li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li>
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<li><a target="_blank" href="development.html">Overall</a> development</li>
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<li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration
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</li>
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@ -28,10 +29,23 @@
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<li><a target="_blank" href="Board/board.html">Board</a> support</li>
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</ul>
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<h1>Payload Development</h1>
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<ul>
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<li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>
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<ul>
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<li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process">EDK II Development Process</a></li>
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<li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20papers">White Papers</a></li>
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<li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github-Quick-Start">SourceForge to Github Quick Start</a></li>
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<li>UEFI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_A.PDF">2.5 Errata A</a></li>
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</ul>
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</li>
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</ul>
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<h1>Documentation</h1>
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<ul>
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<li><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI 6.0 Specification</a></li>
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<li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li>
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<li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li>
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<li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
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</ul>
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