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mb/ocp/tiogapass: Use macro to configure IIO 

Use macros to configure each of the IIO ports instead of an array
of some unknown parameters. This will clean up the code and make
it easier to read.

Tested with BUILD_TIMELESS=1, Tioga Pass, remains identical.

Change-Id: I2911992435a6c93624525426d56212f821abb866
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43502
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maxim Polyakov 2020-07-15 16:29:08 +03:00 committed by Angel Pons
parent 8be5b59a41
commit 4eed5e9057
1 changed files with 38 additions and 41 deletions
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79
src/mainboard/ocp/tiogapass/include/skxsp_tp_iio.h
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@ -39,51 +39,48 @@ static const UPD_IIO_BIFURCATION_DATA_ENTRY tp_iio_bifur_table[] = {
{ Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */ { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxxxx }, /* No MCP */
}; };
#define CFG_UPD_PORT(port, hide) \
{ \
.PortIndex = port, \
.HidePort = hide, \
.DeEmphasis = 0x00, \
.PortLinkSpeed = PcieAuto, \
.MaxPayload = 0x00, \
.DfxDnTxPreset = 0xFF, \
.DfxRxPreset = 0xFF, \
.DfxUpTxPreset = 0xFF, \
.Sris = 0x00, \
.PcieCommonClock = 0x00, \
.NtbPpd = NTB_PORT_TRANSPARENT, \
.NtbSplitBar = 0x00, \
.NtbBarSizePBar23 = 0x16, \
.NtbBarSizePBar4 = 0x16, \
.NtbBarSizePBar5 = 0x16, \
.NtbBarSizePBar45 = 0x16, \
.NtbBarSizeSBar23 = 0x16, \
.NtbBarSizeSBar4 = 0x16, \
.NtbBarSizeSBar5 = 0x16, \
.NtbBarSizeSBar45 = 0x16, \
.NtbSBar01Prefetch = 0x00, \
.NtbXlinkCtlOverride = 0x03, \
}
/* /*
* Standard Tioga Pass Iio PCIe Port Table * Standard Tioga Pass Iio PCIe Port Table
*/ */
static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = { static const UPD_PCI_PORT_CONFIG tp_iio_pci_port_skt0[] = {
// PortIndex | HidePort | DeEmphasis | PortLinkSpeed | MaxPayload | CFG_UPD_PORT(PORT_1A, NOT_HIDE),
// DfxDnTxPreset | DfxRxPreset | DfxUpTxPreset | Sris | PcieCommonClock | NtbPpd | CFG_UPD_PORT(PORT_1B, HIDE),
// NtbSplitBar | NtbBarSizePBar23 | NtbBarSizePBar4 | NtbBarSizePBar5 | CFG_UPD_PORT(PORT_1C, HIDE),
// NtbBarSizePBar45 | NtbBarSizeSBar23 | NtbBarSizeSBar4 | NtbBarSizeSbar5 | CFG_UPD_PORT(PORT_1D, HIDE),
// NtbBarSizeSBar45 | NtbSBar01Prefetch | NtbXlinkCtlOverride CFG_UPD_PORT(PORT_2A, NOT_HIDE),
{ PORT_1A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, CFG_UPD_PORT(PORT_2B, HIDE),
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, CFG_UPD_PORT(PORT_2C, HIDE),
0x16, 0x00, 0x03 }, CFG_UPD_PORT(PORT_2D, HIDE),
{ PORT_1B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, CFG_UPD_PORT(PORT_3A, NOT_HIDE),
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, CFG_UPD_PORT(PORT_3B, HIDE),
0x16, 0x00, 0x03 }, CFG_UPD_PORT(PORT_3C, NOT_HIDE),
{ PORT_1C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00, CFG_UPD_PORT(PORT_3D, HIDE),
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_1D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_2A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_2B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_2C, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_2D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_3A, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_3B, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_3C, NOT_HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
{ PORT_3D, HIDE, 0x00, PcieAuto, 0x0, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
NTB_PORT_TRANSPARENT, 0x00, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16, 0x16,
0x16, 0x00, 0x03 },
}; };
/* /*