GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/rex/var/screebo: set HBR smbus pin as NC 

Since GPP_C03/GPP_04 are floating in HW design, we set HBR smbus pin
as NC, in case it prevents ese and cse from entering suspend.

BUG=b:283053968
TEST=Verified on screebo non-TBT SKU, suspend and resume works.

Change-Id: I401db32f0286de61ce3ab6c61de9528ec76cb51d
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75643
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Simon Zhou 2023-06-02 13:06:06 +08:00 committed by Felix Held
parent 3ea0202925
commit 4eee50642f
1 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/mainboard/google/rex/variants/screebo/gpio.c
View File

@ -102,9 +102,9 @@ static const struct pad_config gpio_table[] = {
/* GPP_C02 : SOC_TCHSCR_SPI_INT_STRAP ==> Component NC */
PAD_NC(GPP_C02, NONE),
/* GPP_C03 : [] ==> SOC_TCP_SMBUS_CLK*/
PAD_CFG_NF_LOCK(GPP_C03, NONE, NF1, LOCK_CONFIG),
PAD_NC(GPP_C03, NONE),
/* GPP_C04 : [] ==> SOC_TCP_SMBUS_SDA*/
PAD_CFG_NF_LOCK(GPP_C04, NONE, NF1, LOCK_CONFIG),
PAD_NC(GPP_C04, NONE),
/* GPP_C05 : [] ==> WWAN_PERST_L_STRAP */
PAD_NC(GPP_C05, NONE),
/* GPP_C06 : [] ==> SOC_TCHSCR_RPT_EN */