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Assign PIRQs in mainboard Config.lb or use the default ones listed in i82801xx_lpc.c. 

Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4251 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Joseph Smith 2009-05-02 21:30:57 +00:00 committed by Joseph Smith
parent 88e71e8859
commit 4f0154c937
2 changed files with 69 additions and 10 deletions
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12
src/southbridge/intel/i82801xx/chip.h
View File

@ -31,6 +31,18 @@
#define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801XX_CHIP_H
struct southbridge_intel_i82801xx_config { struct southbridge_intel_i82801xx_config {
/**
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
*/
uint8_t pirqa_routing;
uint8_t pirqb_routing;
uint8_t pirqc_routing;
uint8_t pirqd_routing;
uint8_t pirqe_routing;
uint8_t pirqf_routing;
uint8_t pirqg_routing;
uint8_t pirqh_routing;
}; };
extern struct chip_operations southbridge_intel_i82801xx_ops; extern struct chip_operations southbridge_intel_i82801xx_ops;

67
src/southbridge/intel/i82801xx/i82801xx_lpc.c
View File

@ -36,6 +36,8 @@
#define NMI_OFF 0 #define NMI_OFF 0
typedef struct southbridge_intel_i82801xx_config config_t;
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control /* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
* 0x00 - 0000 = Reserved * 0x00 - 0000 = Reserved
* 0x01 - 0001 = Reserved * 0x01 - 0001 = Reserved
@ -66,7 +68,11 @@
#define PIRQG 0x0A #define PIRQG 0x0A
#define PIRQH 0x0B #define PIRQH 0x0B
/* Use 0x0ef8 for a bitmap to cover all these IRQ's. */ /*
* Use 0x0ef8 for a bitmap to cover all these IRQ's.
* Use the defined IRQ values above or set mainboard
* specific IRQ values in your mainboards Config.lb.
*/
void i82801xx_enable_apic(struct device *dev) void i82801xx_enable_apic(struct device *dev)
{ {
@ -114,18 +120,59 @@ void i82801xx_enable_serial_irqs(struct device *dev)
static void i82801xx_pirq_init(device_t dev, uint16_t ich_model) static void i82801xx_pirq_init(device_t dev, uint16_t ich_model)
{ {
/* Route PIRQA - PIRQD. */ /* Get the chip configuration */
pci_write_config8(dev, PIRQA_ROUT, PIRQA); config_t *config = dev->chip_info;
pci_write_config8(dev, PIRQB_ROUT, PIRQB);
pci_write_config8(dev, PIRQC_ROUT, PIRQC); if (config->pirqa_routing) {
pci_write_config8(dev, PIRQD_ROUT, PIRQD); pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
} else {
pci_write_config8(dev, PIRQA_ROUT, PIRQA);
}
if (config->pirqb_routing) {
pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
} else {
pci_write_config8(dev, PIRQB_ROUT, PIRQB);
}
if (config->pirqc_routing) {
pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
} else {
pci_write_config8(dev, PIRQC_ROUT, PIRQC);
}
if (config->pirqd_routing) {
pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
} else {
pci_write_config8(dev, PIRQD_ROUT, PIRQD);
}
/* Route PIRQE - PIRQH (for ICH2-ICH9). */ /* Route PIRQE - PIRQH (for ICH2-ICH9). */
if (ich_model >= 0x2440) { if (ich_model >= 0x2440) {
pci_write_config8(dev, PIRQE_ROUT, PIRQE);
pci_write_config8(dev, PIRQF_ROUT, PIRQF); if (config->pirqe_routing) {
pci_write_config8(dev, PIRQG_ROUT, PIRQG); pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
pci_write_config8(dev, PIRQH_ROUT, PIRQH); } else {
pci_write_config8(dev, PIRQE_ROUT, PIRQE);
}
if (config->pirqf_routing) {
pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
} else {
pci_write_config8(dev, PIRQF_ROUT, PIRQF);
}
if (config->pirqg_routing) {
pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
} else {
pci_write_config8(dev, PIRQG_ROUT, PIRQG);
}
if (config->pirqh_routing) {
pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
} else {
pci_write_config8(dev, PIRQH_ROUT, PIRQH);
}
} }
} }