arch/x86,soc/intel: Drop RESET_ON_INVALID_RAMSTAGE_CACHE
If stage cache is enabled, we should not allow S3 resume to load firmware from non-volatile memory. This also adds board reset for failing to load postcar from stage cache. Change-Id: Ib6cc7ad0fe9dcdf05b814d324b680968a2870f23 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -2,7 +2,6 @@ CONFIG_VENDOR_GOOGLE=y
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CONFIG_BOARD_GOOGLE_MEEP=y
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CONFIG_PAYLOAD_NONE=y
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CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_SMM=y
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CONFIG_USE_BLOBS=y
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@ -3,7 +3,6 @@ CONFIG_VENDOR_GOOGLE=y
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CONFIG_BOARD_GOOGLE_REEF=y
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CONFIG_CHROMEOS=y
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CONFIG_ADD_FSP_BINARIES=y
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CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE=y
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CONFIG_ELOG_GSMI=y
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CONFIG_ELOG_BOOT_COUNT=y
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CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
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@ -19,6 +19,7 @@
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <program_loading.h>
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#include <reset.h>
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#include <rmodule.h>
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#include <romstage_handoff.h>
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#include <stage_cache.h>
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@ -208,6 +209,12 @@ void postcar_enable_tseg_cache(struct postcar_frame *pcf)
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MTRR_TYPE_WRBACK);
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}
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static void postcar_cache_invalid(void)
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{
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printk(BIOS_ERR, "postcar cache invalid.\n");
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board_reset();
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}
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void run_postcar_phase(struct postcar_frame *pcf)
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{
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struct prog prog =
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@ -222,6 +229,9 @@ void run_postcar_phase(struct postcar_frame *pcf)
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parameters between S3 resume and normal boot. On the
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platforms where the values are the same it's a nop. */
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finalize_load(prog.arg, pcf->stack);
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if (prog_entry(&prog) == NULL)
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postcar_cache_invalid();
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} else
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load_postcar_cbfs(&prog, pcf);
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@ -35,16 +35,4 @@ config IED_REGION_SIZE
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config SMM_RESERVED_SIZE
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hex
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default 0x100000
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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help
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The haswell romstage code caches the loaded ramstage program
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in SMM space. On S3 wake the romstage will copy over a fresh
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ramstage that was cached in the SMM space. This option determines
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the action to take when the ramstage cache is invalid. If selected
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the system will reset otherwise the ramstage will be reloaded from
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cbfs.
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endif
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@ -82,10 +82,6 @@ config USE_GENERIC_FSP_CAR_INC
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The chipset can select this to use a generic cache_as_ram.inc file
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that should be good for all FSP based platforms.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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config SKIP_FSP_CAR
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def_bool n
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help
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@ -117,10 +117,6 @@ config FSP_TEMP_RAM_SIZE
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stack with coreboot/bootloader.
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Sync this value with Platform FSP integration guide recommendation.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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config FSP2_0_USES_TPM_MRC_HASH
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bool
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depends on TPM1 || TPM2
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@ -83,14 +83,6 @@ fail:
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int __weak prog_locate_hook(struct prog *prog) { return 0; }
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static void ramstage_cache_invalid(void)
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{
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printk(BIOS_ERR, "ramstage cache invalid.\n");
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if (CONFIG(RESET_ON_INVALID_RAMSTAGE_CACHE)) {
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board_reset();
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}
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}
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static void run_ramstage_from_resume(struct prog *ramstage)
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{
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if (!romstage_handoff_is_resume())
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@ -105,7 +97,9 @@ static void run_ramstage_from_resume(struct prog *ramstage)
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printk(BIOS_DEBUG, "Jumping to image.\n");
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prog_run(ramstage);
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}
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ramstage_cache_invalid();
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printk(BIOS_ERR, "ramstage cache invalid.\n");
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board_reset();
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}
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static int load_relocatable_ramstage(struct prog *ramstage)
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@ -74,8 +74,8 @@ ramstage-y += xhci.c
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postcar-y += mmap_boot.c
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postcar-y += spi.c
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postcar-y += i2c.c
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postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
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postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
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postcar-y += heci.c
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postcar-y += reset.c
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postcar-y += uart.c
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postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c
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@ -124,17 +124,6 @@ config DCACHE_BSP_STACK_SIZE
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hex
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default 0x2000
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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help
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The baytrail romstage code caches the loaded ramstage program
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in SMM space. On S3 wake the romstage will copy over a fresh
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ramstage that was cached in the SMM space. This option determines
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the action to take when the ramstage cache is invalid. If selected
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the system will reset otherwise the ramstage will be reloaded from
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cbfs.
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config ENABLE_BUILTIN_COM1
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bool "Enable builtin COM1 Serial Port"
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default n
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@ -104,17 +104,6 @@ config DCACHE_RAM_SIZE
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and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
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must add up to a power of 2.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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help
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The haswell romstage code caches the loaded ramstage program
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in SMM space. On S3 wake the romstage will copy over a fresh
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ramstage that was cached in the SMM space. This option determines
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the action to take when the ramstage cache is invalid. If selected
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the system will reset otherwise the ramstage will be reloaded from
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cbfs.
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config ENABLE_BUILTIN_COM1
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bool "Enable builtin COM1 Serial Port"
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default n
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@ -166,16 +166,6 @@ config PRE_GRAPHICS_DELAY
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VBIOS. On those systems we need to wait for a bit before executing
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the VBIOS.
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config RESET_ON_INVALID_RAMSTAGE_CACHE
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bool "Reset the system on S3 wake when ramstage cache invalid."
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default n
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help
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The romstage code caches the loaded ramstage program in SMM space.
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On S3 wake the romstage will copy over a fresh ramstage that was
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cached in the SMM space. This option determines the action to take
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when the ramstage cache is invalid. If selected the system will
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reset otherwise the ramstage will be reloaded from cbfs.
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config INTEL_PCH_UART_CONSOLE
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bool "Use Serial IO UART for console"
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default n
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