GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720 

Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.

BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff

With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff

Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.

Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Simon Glass 2018-05-23 15:34:04 -06:00 committed by Martin Roth
parent 57ccb9c5e8
commit 4f16049f17
3 changed files with 33 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

26
src/drivers/generic/bayhub/bh720.c
View File

@ -24,16 +24,24 @@
enum {
BH720_PROTECT = 0xd0,
BH720_PROTECT_LOCK_OFF = 0,
BH720_PROTECT_LOCK_ON = BIT(0),
BH720_PROTECT_OFF = 0,
BH720_PROTECT_ON = 1,
BH720_RTD3_L1 = 0x3e0,
BH720_RTD3_L1_DISABLE_L1 = BIT(28),
BH720_PROTECT_ON = BIT(31),
BH720_LINK_CTRL = 0x90,
BH720_LINK_CTRL_L0_ENABLE = BIT(0),
BH720_LINK_CTRL_L1_ENABLE = BIT(1),
BH720_LINK_CTRL_CLKREQ = BIT(8),
BH720_MISC2 = 0xf0,
BH720_MISC2_ASPM_DISABLE = BIT(0),
BH720_MISC2_APSM_CLKREQ_L1 = BIT(7),
BH720_MISC2_APSM_PHY_L1 = BIT(10),
BH720_MISC2_APSM_MORE = BIT(12),
BH720_RTD3_L1 = 0x3e0,
BH720_RTD3_L1_DISABLE_L1 = BIT(28),
};
static void bh720_init(struct device *dev)
@ -47,13 +55,19 @@ static void bh720_init(struct device *dev)
* This procedure for enabling power-saving mode is from the
* BayHub BIOS Implementation Guideline document.
*/
pci_write_config32(dev, BH720_PROTECT, BH720_PROTECT_OFF);
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_OFF | BH720_PROTECT_LOCK_OFF);
pci_or_config32(dev, BH720_RTD3_L1, BH720_RTD3_L1_DISABLE_L1);
pci_or_config32(dev, BH720_LINK_CTRL,
BH720_LINK_CTRL_L0_ENABLE |
BH720_LINK_CTRL_L1_ENABLE);
pci_or_config32(dev, BH720_LINK_CTRL, BH720_LINK_CTRL_CLKREQ);
pci_write_config32(dev, BH720_PROTECT, BH720_PROTECT_ON);
pci_update_config32(dev, BH720_MISC2, ~BH720_MISC2_ASPM_DISABLE,
BH720_MISC2_APSM_CLKREQ_L1 |
BH720_MISC2_APSM_PHY_L1);
pci_write_config32(dev, BH720_PROTECT,
BH720_PROTECT_ON | BH720_PROTECT_LOCK_ON);
printk(BIOS_INFO, "BayHub BH720: Power-saving enabled (link_ctrl=%#x)\n",
pci_read_config32(dev, BH720_LINK_CTRL));
}

7
src/mainboard/google/kahlee/mainboard.c
View File

@ -18,6 +18,7 @@
#include <console/console.h>
#include <device/device.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <amdblocks/agesawrapper.h>
#include <amdblocks/amd_pci_util.h>
#include <cbmem.h>
@ -143,6 +144,12 @@ static void mainboard_init(void *chip_info)
/* Set GenIntDisable so that GPIO 90 is configured as a GPIO. */
pm_write8(PM_PCIB_CFG, pm_read8(PM_PCIB_CFG) | PM_GENINT_DISABLE);
/* Set low-power mode for BayHub eMMC bridge's PCIe clock. */
clrsetbits_le32((uint32_t *)(MISC_MMIO_BASE + GPP_CLK_CNTRL),
GPP_CLK2_CLOCK_REQ_MAP_MASK,
GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 <<
GPP_CLK2_CLOCK_REQ_MAP_SHIFT);
}
/*************************************************

6
src/soc/amd/stoneyridge/include/soc/southbridge.h
View File

@ -356,6 +356,12 @@
#define PM1_LIMIT 16
#define GPE0_LIMIT 28
/* Bit definitions for MISC_MMIO_BASE register GPPClkCntrl */
#define GPP_CLK_CNTRL 0
#define GPP_CLK2_CLOCK_REQ_MAP_SHIFT 8
#define GPP_CLK2_CLOCK_REQ_MAP_MASK (0xf << GPP_CLK2_CLOCK_REQ_MAP_SHIFT)
#define GPP_CLK2_CLOCK_REQ_MAP_CLK_REQ2 3
struct stoneyridge_aoac {
int enable;
int status;