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fixup. SMP works fine. 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich 2003-08-05 23:31:26 +00:00
parent 0c3fd559ec
commit 4f1a6975ef
3 changed files with 41 additions and 31 deletions
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38
src/mainboard/arima/hdama/irq_tables.c
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@ -7,25 +7,37 @@
#include <arch/pirq_routing.h>
const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*7, /* there can be total 7 devices on the bus */
32+16*18, /* there can be total 18 devices on the bus */
0, /* Where the interrupt router lies (bus) */
(5<<3)|3, /* Where the interrupt router lies (dev) */
0xc20, /* IRQs devoted exclusively to PCI usage */
0x3b, /* Where the interrupt router lies (dev) */
0, /* IRQs devoted exclusively to PCI usage */
0x1022, /* Vendor */
0x746b, /* Device */
0x7400, /* Device */
0, /* Crap (miniport) */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xdf, /* u8 checksum , mod 256 checksum must give zero */
{ /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x02, (5<<3)|0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}}, 0x02, 0x00},
{0x02, (6<<3)|0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}}, 0x03, 0x00},
{0x02, (7<<3)|0, {{0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}}, 0x04, 0x00},
{0x02, (1<<3)|1, {{0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}, {0x01, 0xdeb8}}, 0x00, 0x00},
{0x00, (5<<3)|1, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00},
{0x00, (2<<3)|0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}}, 0x00, 0x00},
{0xff, 0xff, {{0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}, {0xff, 0xffff}}, 0xff, 0xff},
0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
{0,0xc0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0,0x50, {{0x1, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x2,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x3, 0},
{0x2,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
{0x2,0x18, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x7, 0},
{0x2,0x20, {{0x4, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0x8, 0},
{0x2,0x28, {{0x2, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xa, 0},
{0,0x58, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x3,0x8, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
{0x3,0x10, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
{0x3,0x18, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x9, 0},
{0,0x30, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0x1,0, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
{0x1,0x28, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
{0x1,0x20, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x6, 0},
{0x1,0x30, {{0x3, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0xb, 0},
{0,0x38, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
{0,0xc8, {{0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}, {0, 0xdef8}}, 0, 0},
}
};

2
src/mainboard/arima/hdama/mainboard.c
View File

@ -23,6 +23,8 @@ enable(struct chip *chip, enum chip_pass pass)
switch (pass) {
default: break;
case CONF_PASS_PRE_BOOT:
break;
}
}

26
targets/arima/hdama/Config.lb
View File

@ -12,6 +12,7 @@ uses CONFIG_COMPRESS
uses CONFIG_IOAPIC
uses CONFIG_ROM_STREAM
uses CONFIG_ROM_STREAM_START
uses CONFIG_SMP
uses CONFIG_UDELAY_TSC
uses CPU_FIXUP
uses ENABLE_FIXED_AND_VARIABLE_MTRRS
@ -23,8 +24,8 @@ uses HAVE_PIRQ_TABLE
uses i586
uses i686
uses INTEL_PPRO_MTRR
uses HEAP_SIZE
uses IRQ_SLOT_COUNT
uses HEAP_SIZE
uses k7
uses k8
uses MAINBOARD_PART_NUMBER
@ -54,8 +55,8 @@ uses CONFIG_CHIP_CONFIGURE
option CONFIG_CHIP_CONFIGURE=1
option MAXIMUM_CONSOLE_LOGLEVEL=7
option DEFAULT_CONSOLE_LOGLEVEL=7
option MAXIMUM_CONSOLE_LOGLEVEL=9
option DEFAULT_CONSOLE_LOGLEVEL=9
option CONFIG_CONSOLE_SERIAL8250=1
option HAVE_OPTION_TABLE=1
@ -78,14 +79,14 @@ option SIO_SYSTEM_CLK_INPUT=0
### Build code to export a programmable irq routing table
###
option HAVE_PIRQ_TABLE=1
option IRQ_SLOT_COUNT=7
option IRQ_SLOT_COUNT=18
#
###
### Build code for SMP support
### Only worry about 2 micro processors
###
##option CONFIG_SMP=1
option MAX_CPUS=1
option CONFIG_SMP=1
option MAX_CPUS=2
#
###
### Build code to setup a generic IOAPIC
@ -111,13 +112,7 @@ option MEMORY_HOLE=0
### processor identification
###
option ENABLE_FIXED_AND_VARIABLE_MTRRS=1
#
###
### Clean up the motherboard id strings
###
#option MAINBOARD_PART_NUMBER="Solo7"
#option MAINBOARD_VENDOR="AMD"
#
###
### Call the final_mainboard_fixup function
###
@ -151,7 +146,7 @@ option CONFIG_COMPRESS=1
option USE_ELF_BOOT=1
## LinuxBIOS C code runs at this location in RAM
option _RAMBASE=0x00100000
option _RAMBASE=0x4000
##
## Use a 64K stack
@ -195,7 +190,8 @@ romimage "fallback"
option CONFIG_ROM_STREAM = 1
option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
mainboard arima/hdama
payload ../../../../opteron_phase1
payload ../../../../tg3--ide_disk.zelf
# payload ../../../../opteron_phase1
end
buildrom ROM_SIZE "normal" "fallback"