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pistachio: increase romstage size 

This change is necessary to support future additions to romstage.

Change-Id: Ibb69994847945c7adbafbf2bc677b33821df8146
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: http://review.coreboot.org/10457
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Ionela Voinescu 2015-06-07 23:07:16 +01:00 committed by Patrick Georgi
parent 42e6856436
commit 4f2f01a8fa
1 changed files with 2 additions and 2 deletions
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4
src/soc/imgtec/pistachio/include/soc/memlayout.ld
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@ -38,8 +38,8 @@ SECTIONS
* and then through the identity mapping in ROM stage.
*/
SRAM_START(0x1a000000)
ROMSTAGE(0x1a005000, 36K)
PRERAM_CBFS_CACHE(0x1a00e000, 72K)
ROMSTAGE(0x1a005000, 40K)
PRERAM_CBFS_CACHE(0x1a00f000, 68K)
SRAM_END(0x1a020000)
/* Bootblock executes out of KSEG0 and sets up the identity mapping.