mb/google/volteer/variant/lindar: Create dynamic fan table mechanism
Add dynamic fan table mechanism for Lindar and Lillipup. Create different fan tables that provided from thermal team. BUG=b:185308432 TEST=Build FW and boot to OS modify CBI test with DPTF tool. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I1b79dbe1ae6ee7aa41cef832b4ee305cc8f4b753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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@ -8,7 +8,10 @@ fw_config
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option USB3_NO_A 5
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option USB3_NO_C 6
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end
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field THERMAL 4 7 end
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field THERMAL 4 7
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option FAN_TABLE_0 0
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option FAN_TABLE_1 1
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end
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field AUDIO 8 10
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option NONE 0
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option MAX98357_ALC5682I_I2S 1
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@ -58,6 +58,119 @@ chip soc/intel/tigerlake
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[PchSerialIoIndexI2C5] = PchSerialIoPci,
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}"
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device domain 0 on
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device ref dptf on
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chip drivers/intel/dptf
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 90, 6700, 220, 2200, },
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[1] = { 80, 5800, 180, 1800, },
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[2] = { 70, 5000, 145, 1450, },
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[3] = { 60, 4900, 115, 1150, },
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[4] = { 50, 3838, 90, 900, },
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[5] = { 40, 2904, 55, 550, },
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[6] = { 30, 2337, 30, 300, },
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[7] = { 20, 1608, 15, 150, },
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[8] = { 10, 800, 10, 100, },
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[9] = { 0, 0, 0, 50, }}"
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 0 on
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probe THERMAL FAN_TABLE_0
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end
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end
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chip drivers/intel/dptf
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## Active Policy
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register "policies.active" = "{
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[0] = {.target = DPTF_CPU,
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.thresholds = {TEMP_PCT(85, 90),
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TEMP_PCT(80, 69),
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TEMP_PCT(75, 56),
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TEMP_PCT(70, 46),
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TEMP_PCT(65, 36),}},
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[1] = {.target = DPTF_TEMP_SENSOR_0,
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.thresholds = {TEMP_PCT(50, 90),
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TEMP_PCT(47, 69),
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TEMP_PCT(45, 56),
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TEMP_PCT(42, 46),
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TEMP_PCT(39, 36),}},
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[2] = {.target = DPTF_TEMP_SENSOR_1,
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.thresholds = {TEMP_PCT(50, 90),
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TEMP_PCT(47, 69),
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TEMP_PCT(45, 56),
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TEMP_PCT(42, 46),
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TEMP_PCT(39, 36),}},
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[3] = {.target = DPTF_TEMP_SENSOR_2,
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.thresholds = {TEMP_PCT(50, 90),
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TEMP_PCT(47, 69),
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TEMP_PCT(45, 56),
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TEMP_PCT(42, 46),
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TEMP_PCT(39, 36),}},
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[4] = {.target = DPTF_TEMP_SENSOR_3,
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.thresholds = {TEMP_PCT(50, 90),
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TEMP_PCT(47, 69),
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TEMP_PCT(45, 56),
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TEMP_PCT(42, 46),
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TEMP_PCT(39, 36),}}}"
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## Passive Policy
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register "policies.passive" = "{
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[0] = DPTF_PASSIVE(CPU, CPU, 95, 5000),
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[1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 65, 6000),
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[2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_0, 65, 6000),
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[3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 65, 6000),
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[4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 65, 6000)}"
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## Critical Policy
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register "policies.critical" = "{
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[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
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[1] = DPTF_CRITICAL(TEMP_SENSOR_0, 75, SHUTDOWN),
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[2] = DPTF_CRITICAL(TEMP_SENSOR_1, 75, SHUTDOWN),
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[3] = DPTF_CRITICAL(TEMP_SENSOR_2, 75, SHUTDOWN),
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[4] = DPTF_CRITICAL(TEMP_SENSOR_3, 75, SHUTDOWN)}"
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## Power Limits Control
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# 3-15W PL1 in 200mW increments, avg over 28-32s interval
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# PL2 ranges from 15 to 60W, avg over 28-32s interval
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register "controls.power_limits" = "{
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.pl1 = {.min_power = 3000,
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.max_power = 15000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 200,},
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.pl2 = {.min_power = 60000,
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.max_power = 60000,
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.time_window_min = 28 * MSECS_PER_SEC,
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.time_window_max = 32 * MSECS_PER_SEC,
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.granularity = 1000,}}"
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## Charger Performance Control (Control, mA)
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register "controls.charger_perf" = "{
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[0] = { 255, 1700 },
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[1] = { 24, 1500 },
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[2] = { 16, 1000 },
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[3] = { 8, 500 }}"
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## Fan Performance Control (Percent, Speed, Noise, Power)
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register "controls.fan_perf" = "{
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[0] = { 100, 5800, 220, 2200, },
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[1] = { 90, 5700, 180, 1800, },
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[2] = { 80, 5050, 145, 1450, },
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[3] = { 70, 4800, 115, 1150, },
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[4] = { 65, 4500, 90, 900, },
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[5] = { 60, 4200, 55, 550, },
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[6] = { 55, 3800, 30, 300, },
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[7] = { 50, 3508, 15, 150, },
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[8] = { 45, 3400, 10, 100, },
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[9] = { 0, 0, 0, 50, }}"
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register "options.fan.fine_grained_control" = "1"
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register "options.fan.step_size" = "2"
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device generic 1 on
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probe THERMAL FAN_TABLE_1
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end
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end
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end
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# Baseboard has these on, so they must be disabled here.
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device ref tbt_pcie_rp0 off end
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device ref tbt_pcie_rp1 off end
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