GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/common/block/sata: Convert DWORD width Read/Write to BYTE width 

As per EDS Sata port implemented register is byte width (bits[3:0]) hence
converting required DWORD based read/write to BYTE width read/write.

TEST=Able to boot from SATA device on CML hatch.

Change-Id: I545b823318bae461137d41a4490117eba7c87330
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34070
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-07-04 16:26:58 +05:30
parent 65f03b7c42
commit 4f61f56be1
1 changed files with 4 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/common/block/sata/sata.c
View File

@ -43,14 +43,14 @@ static void *sata_get_ahci_bar(struct device *dev)
static void sata_final(struct device *dev)
{
void *ahcibar = sata_get_ahci_bar(dev);
u32 port_impl, temp;
u8 port_impl, temp;
/* Set Bus Master */
temp = pci_read_config32(dev, PCI_COMMAND);
pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);
/* Read Ports Implemented (GHC_PI) */
port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED);
port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED);
if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT))
port_impl = ~port_impl;
@ -58,9 +58,9 @@ static void sata_final(struct device *dev)
port_impl &= 0x07; /* bit 0-2 */
/* Port enable */
temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS);
temp = pci_read_config8(dev, SATA_PCI_CFG_PORT_CTL_STS);
temp |= port_impl;
pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp);
pci_write_config8(dev, SATA_PCI_CFG_PORT_CTL_STS, temp);
}
static struct device_operations sata_ops = {