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soc/intel/skylake: Update 64 bit SA DRAM bit fields as per datasheet 

This patch updates SA DRAM registers bit definitions as per
SKL datasheet vol 2, doc 332688.

TEST=Build and boot EVE and Soraka to OS.

Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2020-01-22 16:05:16 +05:30
parent 36eb500994
commit 4f65b87cf4
1 changed files with 5 additions and 4 deletions
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9
src/soc/intel/skylake/acpi/systemagent.asl
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@ -32,26 +32,27 @@ Device (MCHC)
Offset(0x40), /* EPBAR (0:0:0:40) */ Offset(0x40), /* EPBAR (0:0:0:40) */
EPEN, 1, /* Enable */ EPEN, 1, /* Enable */
, 11, , 11,
EPBR, 20, /* EPBAR [31:12] */ EPBR, 27, /* EPBAR [38:12] */
Offset(0x48), /* MCHBAR (0:0:0:48) */ Offset(0x48), /* MCHBAR (0:0:0:48) */
MHEN, 1, /* Enable */ MHEN, 1, /* Enable */
, 14, , 14,
MHBR, 17, /* MCHBAR [31:15] */ MHBR, 24, /* MCHBAR [38:15] */
Offset(0x60), /* PCIEXBAR (0:0:0:60) */ Offset(0x60), /* PCIEXBAR (0:0:0:60) */
PXEN, 1, /* Enable */ PXEN, 1, /* Enable */
PXSZ, 2, /* PCI Express Size */ PXSZ, 2, /* PCI Express Size */
, 23, , 23,
PXBR, 6, /* PCI Express BAR [31:26] */ PXBR, 13, /* PCI Express BAR [38:26] */
Offset(0x68), /* DMIBAR (0:0:0:68) */ Offset(0x68), /* DMIBAR (0:0:0:68) */
DIEN, 1, /* Enable */ DIEN, 1, /* Enable */
, 11, , 11,
DIBR, 20, /* DMIBAR [31:12] */ DIBR, 27, /* DMIBAR [38:12] */
Offset (0x70), /* ME Base Address */ Offset (0x70), /* ME Base Address */
MEBA, 64, MEBA, 64,
Offset (0xa0), Offset (0xa0),
TOM, 64, /* Top of Used Memory */ TOM, 64, /* Top of Used Memory */
TUUD, 64, /* Top of Upper Used Memory */ TUUD, 64, /* Top of Upper Used Memory */