soc/intel/common: Add function to DLOCK PR registers
Add a function in FAST_SPI library to discrete lock the PR registers 0 to 4. BUG=none BRANCH=none TEST=Build and boot poppy Change-Id: I46e1948315ea9489932efdf7d60d6d78ab3948a6 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/21063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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@ -152,6 +152,23 @@ void fast_spi_lock_bar(void)
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write16(spibar + SPIBAR_HSFSTS_CTL, hsfs);
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}
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/*
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* Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the
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* FAST_SPI Protected Range (PR) registers.
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*/
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void fast_spi_pr_dlock(void)
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{
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void *spibar = fast_spi_get_bar();
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uint32_t dlock;
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dlock = read32(spibar + SPIBAR_DLOCK);
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dlock |= (SPIBAR_DLOCK_PR0LOCKDN | SPIBAR_DLOCK_PR1LOCKDN
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| SPIBAR_DLOCK_PR2LOCKDN | SPIBAR_DLOCK_PR3LOCKDN
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| SPIBAR_DLOCK_PR4LOCKDN);
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write32(spibar + SPIBAR_DLOCK, dlock);
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}
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/*
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* Set FAST_SPIBAR Soft Reset Data Register value.
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*/
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@ -34,6 +34,7 @@
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#define SPIBAR_BFPREG 0x00
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#define SPIBAR_HSFSTS_CTL 0x04
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#define SPIBAR_FADDR 0x08
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#define SPIBAR_DLOCK 0x0c
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#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4)
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#define SPIBAR_FPR_BASE 0x84
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#define SPIBAR_FPR(n) 0x84 + (4 * n))
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@ -87,6 +88,13 @@
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/* Bit definitions for FADDR (0x08) register */
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#define SPIBAR_FADDR_MASK 0x7FFFFFF
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/* Bit definitions for DLOCK (0x0C) register */
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#define SPIBAR_DLOCK_PR0LOCKDN (1 << 8)
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#define SPIBAR_DLOCK_PR1LOCKDN (1 << 9)
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#define SPIBAR_DLOCK_PR2LOCKDN (1 << 10)
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#define SPIBAR_DLOCK_PR3LOCKDN (1 << 11)
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#define SPIBAR_DLOCK_PR4LOCKDN (1 << 12)
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/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
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#define SPIBAR_FDATA_FIFO_SIZE 0x40
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@ -48,6 +48,11 @@ void fast_spi_set_opcode_menu(void);
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* Lock FAST_SPIBAR.
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*/
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void fast_spi_lock_bar(void);
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/*
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* Set FAST_SPIBAR + DLOCK (0x0C) register bits to discrete lock the
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* FAST_SPI Protected Range (PR) registers.
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*/
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void fast_spi_pr_dlock(void);
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/*
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* Set FAST_SPIBAR Soft Reset Data Register value.
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*/
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