treewide: Rename Sabrina to Mendocino

'Mendocino' was an embargoed name and could previously not be used
in references to Skyrim.  coreboot has references to sabrina both
in directory structure and in files. This will make life difficult
for people looking for Mendocino support in the long term. The code
name should be replaced with "mendocino".

BUG=b:239072117
TEST=Builds

Cq-Depend: chromium:3764023
Cq-Depend: chromium:3763392
Cq-Depend: chrome-internal:4876777

Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I2d0f76fde07a209a79f7e1596cc8064e53f06ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>

MAINTAINERS

@@ -656,7 +656,7 @@ S:	Maintained
 F:	src/soc/amd/picasso/
 F:	src/vendorcode/amd/fsp/picasso/
 
-AMD Sabrina
+AMD Mendocino
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>
 M:	Felix Held <felix-coreboot@felixheld.de>
 M:	Jason Glenesk <jason.glenesk@gmail.com>
@@ -664,8 +664,8 @@ M:	Raul E Rangel <rrangel@chromium.org>
 M:	Fred Reitberger <reitbergerfred@gmail.com>
 M:	Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
 S:	Maintained
-F:	src/soc/amd/sabrina/
+F:	src/soc/amd/mendocino/
-F:	src/vendorcode/amd/fsp/sabrina/
+F:	src/vendorcode/amd/fsp/mendocino/
 
 AMD Stoneyridge
 M:	Marshall Dawson <marshalldawson3rd@gmail.com>

src/mainboard/amd/chausie/Kconfig

@@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
 	def_bool y
 	select BOARD_ROMSIZE_KB_16384
 	select EC_ACPI
-	select SOC_AMD_SABRINA
+	select SOC_AMD_MENDOCINO
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select AMD_SOC_CONSOLE_UART
 	select MAINBOARD_HAS_CHROMEOS
@@ -74,7 +74,7 @@ config RO_REGION_ONLY
 	string
 	depends on VBOOT_SLOTS_RW_AB || VBOOT_SLOTS_RW_A
 	# Add the EFS and EC to the RO region only
-	# This is a chausie-specific override of soc/amd/sabrina/Kconfig
+	# This is a chausie-specific override of soc/amd/mendocino/Kconfig
 	default "apu/amdfw apu/ecfw"
 
 config CHROMEOS

src/mainboard/amd/chausie/devicetree.cb

@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
-chip soc/amd/sabrina
+chip soc/amd/mendocino
 	register "common_config.espi_config" = "{
 		.std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN | ESPI_DECODE_IO_0X2E_0X2F_EN | ESPI_DECODE_IO_0X60_0X64_EN,
 		.generic_io_range[0] = {

src/mainboard/google/skyrim/Kconfig

@@ -36,7 +36,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select MAINBOARD_HAS_CHROMEOS
 	select MAINBOARD_HAS_TPM2
 	select PSP_DISABLE_POSTCODES   # TODO re-enable PSP postcodes later (b/227199049)
-	select SOC_AMD_SABRINA
+	select SOC_AMD_MENDOCINO
 	select SOC_AMD_COMMON_BLOCK_USE_ESPI
 	select TPM_GOOGLE_TI50
 

src/mainboard/google/skyrim/variants/baseboard/devicetree.cb

@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
-chip soc/amd/sabrina
+chip soc/amd/mendocino
 
 	# eSPI Configuration
 	register "common_config.espi_config" = "{
@@ -213,4 +213,4 @@ chip soc/amd/sabrina
 
 		device generic 3 on end
 	end
-end	# chip soc/amd/sabrina
+end	# chip soc/amd/mendocino

src/mainboard/google/skyrim/variants/skyrim/overridetree.cb

@@ -26,7 +26,7 @@ fw_config
 	end
 end
 
-chip soc/amd/sabrina
+chip soc/amd/mendocino
 	device domain 0 on
 		device ref gpp_bridge_a on  # Internal GPP Bridge 0 to Bus A
 			device ref xhci_1 on # XHCI1 controller
@@ -241,4 +241,4 @@ chip soc/amd/sabrina
 		end
 	end # UART1
 
-end	# chip soc/amd/sabrina
+end	# chip soc/amd/mendocino

src/soc/amd/common/block/acp/Kconfig

@@ -8,4 +8,4 @@ config SOC_AMD_COMMON_BLOCK_ACP_GEN2
 	bool
 	help
 	  Select this option to perform Audio Co-Processor(ACP) configuration.
-	  Used by the ACP in AMD sabrina (family 17h) and possibly newer CPUs.
+	  Used by the ACP in AMD mendocino (family 17h) and possibly newer CPUs.

src/soc/amd/common/block/include/amdblocks/psp_efs.h

@@ -16,7 +16,7 @@
 #elif CONFIG(SOC_AMD_PICASSO)
   #define SPI_MODE_FIELD spi_readmode_f17_mod_00_2f
   #define SPI_SPEED_FIELD  spi_fastspeed_f17_mod_00_2f
-#elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_SABRINA)
+#elif CONFIG(SOC_AMD_CEZANNE) | CONFIG(SOC_AMD_MENDOCINO)
   #define SPI_MODE_FIELD spi_readmode_f17_mod_30_3f
   #define SPI_SPEED_FIELD spi_fastspeed_f17_mod_30_3f
 #else

src/soc/amd/common/block/lpc/espi_def.h

@@ -25,7 +25,7 @@
 #define  ESPI_WDG_EN				(1 << 0)
 
 #define ESPI_GLOBAL_CONTROL_1			0x34
-#define  ESPI_ALERT_ENABLE			(1 << 20) /* Sabrina and later SoCs */
+#define  ESPI_ALERT_ENABLE			(1 << 20) /* Mendocino and later SoCs */
 #define  ESPI_RGCMD_INT_MAP_SHIFT		13
 #define  ESPI_RGCMD_INT_MAP_MASK		(0x1f << ESPI_RGCMD_INT_MAP_SHIFT)
 #define    ESPI_RGCMD_INT(irq)			((irq) << ESPI_RGCMD_INT_MAP_SHIFT)

src/soc/amd/mendocino/Kconfig

@@ -5,11 +5,11 @@
 config SOC_AMD_REMBRANDT_BASE
 	bool
 
-config SOC_AMD_SABRINA
+config SOC_AMD_MENDOCINO
 	bool
 	select SOC_AMD_REMBRANDT_BASE
 	help
-	  AMD Sabrina support
+	  AMD Mendocino support
 
 config SOC_AMD_REMBRANDT
 	bool
@@ -99,8 +99,8 @@ config ARCH_ALL_STAGES_X86
 
 config CHIPSET_DEVICETREE
 	string
-	default "soc/amd/sabrina/chipset_sabrina.cb" if SOC_AMD_SABRINA
+	default "soc/amd/mendocino/chipset_mendocino.cb" if SOC_AMD_MENDOCINO
-	default "soc/amd/sabrina/chipset_rembrandt.cb"
+	default "soc/amd/mendocino/chipset_rembrandt.cb"
 
 config EARLY_RESERVED_DRAM_BASE
 	hex
@@ -247,7 +247,7 @@ config ECAM_MMCONF_BUS_NUMBER
 
 config MAX_CPUS
 	int
-	default 8 if SOC_AMD_SABRINA
+	default 8 if SOC_AMD_MENDOCINO
 	default 16
 	help
 	  Maximum number of threads the platform can have.
@@ -355,7 +355,7 @@ comment "AMD Firmware Directory Table set to location for 16MB ROM"
 
 config AMDFW_CONFIG_FILE
 	string "AMD PSP Firmware config file"
-	default "src/soc/amd/sabrina/fw.cfg"
+	default "src/soc/amd/mendocino/fw.cfg"
 	help
 	  Specify the path/location of AMD PSP Firmware config file.
 

src/soc/amd/mendocino/Makefile.inc

@@ -2,7 +2,7 @@
 
 # TODO: Check if this is still correct
 
-ifeq ($(CONFIG_SOC_AMD_SABRINA),y)
+ifeq ($(CONFIG_SOC_AMD_MENDOCINO),y)
 
 subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage
 
@@ -52,9 +52,9 @@ smm-y		+= smihandler.c
 smm-y		+= smu.c
 smm-$(CONFIG_DEBUG_SMI) += uart.c
 
-CPPFLAGS_common += -I$(src)/soc/amd/sabrina/include
+CPPFLAGS_common += -I$(src)/soc/amd/mendocino/include
-CPPFLAGS_common += -I$(src)/soc/amd/sabrina/acpi
+CPPFLAGS_common += -I$(src)/soc/amd/mendocino/acpi
-CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/sabrina
+CPPFLAGS_common += -I$(src)/vendorcode/amd/fsp/mendocino
 
 MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
 
@@ -69,7 +69,7 @@ MAINBOARD_BLOBS_DIR:=$(top)/3rdparty/blobs/mainboard/$(MAINBOARDDIR)
 $(if $(CONFIG_AMD_FWM_POSITION_INDEX), ,\
      $(error Invalid AMD firmware position index. Check if the board sets a valid ROM size))
 
-SABRINA_FWM_POSITION=$(call int-add, \
+MENDOCINO_FWM_POSITION=$(call int-add, \
 	$(call int-subtract, 0xffffffff \
 	$(call int-shift-left, \
 	0x80000 $(CONFIG_AMD_FWM_POSITION_INDEX))) 0x20000 1)
@@ -78,11 +78,11 @@ SABRINA_FWM_POSITION=$(call int-add, \
 # Building the cbfs image will fail if the offset isn't large enough
 AMD_FW_AB_POSITION := 0x40
 
-SABRINA_FW_A_POSITION=$(call int-add, \
+MENDOCINO_FW_A_POSITION=$(call int-add, \
 	$(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_A_START" {print $$3}' $(obj)/fmap_config.h) \
 	$(AMD_FW_AB_POSITION))
 
-SABRINA_FW_B_POSITION=$(call int-add, \
+MENDOCINO_FW_B_POSITION=$(call int-add, \
 	$(shell awk '$$2 == "FMAP_SECTION_FW_MAIN_B_START" {print $$3}' $(obj)/fmap_config.h) \
 	$(AMD_FW_AB_POSITION))
 #
@@ -222,7 +222,7 @@ AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \
 		$(OPT_EFS_SPI_SPEED) \
 		$(OPT_EFS_SPI_MICRON_FLAG) \
 		--config $(CONFIG_AMDFW_CONFIG_FILE) \
-		--soc-name "Sabrina" \
+		--soc-name "Mendocino" \
 		--flashsize $(CONFIG_ROM_SIZE) \
 		$(OPT_RECOVERY_AB_SINGLE_COPY)
 
@@ -243,7 +243,7 @@ $(obj)/amdfw.rom:	$(call strip_quotes, $(PSP_BIOSBIN_FILE)) \
 		$(OPT_APOB_NV_BASE) \
 		$(OPT_VERSTAGE_FILE) \
 		$(OPT_VERSTAGE_SIG_FILE) \
-		--location $(shell printf "%#x" $(SABRINA_FWM_POSITION)) \
+		--location $(shell printf "%#x" $(MENDOCINO_FWM_POSITION)) \
 		--output $@
 
 $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS)
@@ -259,7 +259,7 @@ $(obj)/amdfw_a.rom: $(obj)/amdfw.rom
 		$(AMDFW_COMMON_ARGS) \
 		$(OPT_APOB_NV_SIZE) \
 		$(OPT_APOB_NV_BASE) \
-		--location $(shell printf "%#x" $(SABRINA_FW_A_POSITION)) \
+		--location $(shell printf "%#x" $(MENDOCINO_FW_A_POSITION)) \
 		--anywhere \
 		--output $@
 
@@ -270,14 +270,14 @@ $(obj)/amdfw_b.rom: $(obj)/amdfw.rom
 		$(AMDFW_COMMON_ARGS) \
 		$(OPT_APOB_NV_SIZE) \
 		$(OPT_APOB_NV_BASE) \
-		--location $(shell printf "%#x" $(SABRINA_FW_B_POSITION)) \
+		--location $(shell printf "%#x" $(MENDOCINO_FW_B_POSITION)) \
 		--anywhere \
 		--output $@
 
 
 cbfs-files-y += apu/amdfw
 apu/amdfw-file := $(obj)/amdfw.rom
-apu/amdfw-position := $(SABRINA_FWM_POSITION)
+apu/amdfw-position := $(MENDOCINO_FWM_POSITION)
 apu/amdfw-type := raw
 
 ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy)
@@ -294,4 +294,4 @@ endif
 
 amd_microcode_bins += $(wildcard ${FIRMWARE_LOCATION}/*UcodePatch_*.bin)
 
-endif # ($(CONFIG_SOC_AMD_SABRINA),y)
+endif # ($(CONFIG_SOC_AMD_MENDOCINO),y)

src/soc/amd/mendocino/acpi.c

@@ -58,7 +58,7 @@ unsigned long acpi_fill_madt(unsigned long current)
  */
 void acpi_fill_fadt(acpi_fadt_t *fadt)
 {
-	const struct soc_amd_sabrina_config *cfg = config_of_soc();
+	const struct soc_amd_mendocino_config *cfg = config_of_soc();
 
 	printk(BIOS_DEBUG, "pm_base: 0x%04x\n", ACPI_IO_BASE);
 

src/soc/amd/mendocino/acpi/globalnvs.asl

@@ -4,7 +4,7 @@
 
 /*
  * NOTE: The layout of the GNVS structure below must match the layout in
- * soc/amd/sabrina/include/soc/nvs.h !!!
+ * soc/amd/mendocino/include/soc/nvs.h !!!
  */
 
 Field (GNVS, ByteAcc, NoLock, Preserve)

src/soc/amd/mendocino/chip.c

@@ -19,7 +19,7 @@
 /* Supplied by i2c.c */
 extern struct device_operations soc_amd_i2c_mmio_ops;
 /* Supplied by uart.c */
-extern struct device_operations sabrina_uart_mmio_ops;
+extern struct device_operations mendocino_uart_mmio_ops;
 
 struct device_operations cpu_bus_ops = {
 	.read_resources	= noop_read_resources,
@@ -62,7 +62,7 @@ static void set_mmio_dev_ops(struct device *dev)
 	case APU_UART2_BASE:
 	case APU_UART3_BASE:
 	case APU_UART4_BASE:
-		dev->ops = &sabrina_uart_mmio_ops;
+		dev->ops = &mendocino_uart_mmio_ops;
 		break;
 	case APU_EMMC_BASE:
 		if (!dev->enabled)
@@ -105,8 +105,8 @@ static void soc_final(void *chip_info)
 	fch_final(chip_info);
 }
 
-struct chip_operations soc_amd_sabrina_ops = {
+struct chip_operations soc_amd_mendocino_ops = {
-	CHIP_NAME("AMD Sabrina SoC")
+	CHIP_NAME("AMD Mendocino SoC")
 	.enable_dev = enable_dev,
 	.init = soc_init,
 	.final = soc_final

src/soc/amd/mendocino/chip.h

@@ -2,8 +2,8 @@
 
 /* TODO: Check if this is still correct */
 
-#ifndef SABRINA_CHIP_H
+#ifndef MENDOCINO_CHIP_H
-#define SABRINA_CHIP_H
+#define MENDOCINO_CHIP_H
 
 #include <amdblocks/chip.h>
 #include <amdblocks/i2c.h>
@@ -12,9 +12,9 @@
 #include <soc/southbridge.h>
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <types.h>
-#include <vendorcode/amd/fsp/sabrina/FspUsb.h>
+#include <vendorcode/amd/fsp/mendocino/FspUsb.h>
 
-struct soc_amd_sabrina_config {
+struct soc_amd_mendocino_config {
 	struct soc_amd_common_config common_config;
 	u8 i2c_scl_reset;
 	struct dw_i2c_bus_config i2c[I2C_CTRLR_COUNT];
@@ -104,4 +104,4 @@ struct soc_amd_sabrina_config {
 	struct usb_phy_config usb_phy;
 };
 
-#endif /* SABRINA_CHIP_H */
+#endif /* MENDOCINO_CHIP_H */

src/soc/amd/mendocino/chipset_mendocino.cb

@@ -1,4 +1,4 @@
-chip soc/amd/sabrina
+chip soc/amd/mendocino
 	device cpu_cluster 0 on
 	end
 	device domain 0 on

src/soc/amd/mendocino/config.c

@@ -9,6 +9,6 @@
 const struct soc_amd_common_config *soc_get_common_config(void)
 {
 	/* config_of_soc calls die() internally if cfg was NULL, so no need to re-check */
-	const struct soc_amd_sabrina_config *cfg = config_of_soc();
+	const struct soc_amd_mendocino_config *cfg = config_of_soc();
 	return &cfg->common_config;
 }

src/soc/amd/mendocino/cpu.c

@@ -78,7 +78,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, SABRINA_A0_CPUID},
+	{ X86_VENDOR_AMD, MENDOCINO_A0_CPUID},
 	{ 0, 0 },
 };
 

src/soc/amd/mendocino/early_fch.c

@@ -24,7 +24,7 @@ static const struct soc_i2c_scl_pin i2c_scl_pins[] = {
 
 static void reset_i2c_peripherals(void)
 {
-	const struct soc_amd_sabrina_config *cfg = config_of_soc();
+	const struct soc_amd_mendocino_config *cfg = config_of_soc();
 	struct soc_i2c_peripheral_reset_info reset_info;
 
 	reset_info.i2c_scl_reset_mask = cfg->i2c_scl_reset & GPIO_I2C_MASK;

src/soc/amd/mendocino/fch.c

@@ -130,7 +130,7 @@ static void fch_init_acpi_ports(void)
 /* configure the general purpose PCIe clock outputs according to the devicetree settings */
 static void gpp_clk_setup(void)
 {
-	const struct soc_amd_sabrina_config *cfg = config_of_soc();
+	const struct soc_amd_mendocino_config *cfg = config_of_soc();
 
 	/* look-up table to be able to iterate over the PCIe clock output settings */
 	const uint8_t gpp_clk_shift_lut[GPP_CLK_OUTPUT_COUNT] = {

src/soc/amd/mendocino/fsp_m_params.c

@@ -13,7 +13,7 @@
 #include <soc/pci_devs.h>
 #include <string.h>
 #include <types.h>
-#include <vendorcode/amd/fsp/sabrina/FspUsb.h>
+#include <vendorcode/amd/fsp/mendocino/FspUsb.h>
 #include "chip.h"
 
 __weak void mb_pre_fspm(FSP_M_CONFIG *mcfg)
@@ -69,7 +69,7 @@ static void fsp_assign_ioapic_upds(FSP_M_CONFIG *mcfg)
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
 	FSP_M_CONFIG *mcfg = &mupd->FspmConfig;
-	const struct soc_amd_sabrina_config *config = config_of_soc();
+	const struct soc_amd_mendocino_config *config = config_of_soc();
 
 	mupd->FspmArchUpd.NvsBufferPtr = (uintptr_t)soc_fill_apob_cache();
 

src/soc/amd/mendocino/i2c.c

@@ -34,7 +34,7 @@ void i2c_set_bar(unsigned int bus, uintptr_t bar)
 
 void soc_i2c_misc_init(unsigned int bus, const struct dw_i2c_bus_config *cfg)
 {
-	const struct soc_amd_sabrina_config *config = config_of_soc();
+	const struct soc_amd_mendocino_config *config = config_of_soc();
 
 	if (bus >= ARRAY_SIZE(config->i2c_pad))
 		return;
@@ -50,7 +50,7 @@ const struct soc_i2c_ctrlr_info *soc_get_i2c_ctrlr_info(size_t *num_ctrlrs)
 
 const struct dw_i2c_bus_config *soc_get_i2c_bus_config(size_t *num_buses)
 {
-	const struct soc_amd_sabrina_config *config = config_of_soc();
+	const struct soc_amd_mendocino_config *config = config_of_soc();
 
 	*num_buses = ARRAY_SIZE(config->i2c);
 	return config->i2c;

src/soc/amd/mendocino/include/soc/acpi.h

@@ -2,8 +2,8 @@
 
 /* TODO: Check if this is still correct */
 
-#ifndef AMD_SABRINA_ACPI_H
+#ifndef AMD_MENDOCINO_ACPI_H
-#define AMD_SABRINA_ACPI_H
+#define AMD_MENDOCINO_ACPI_H
 
 #include <acpi/acpi.h>
 #include <amdblocks/acpi.h>
@@ -20,4 +20,4 @@
 uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current,
 				  acpi_rsdp_t *rsdp);
 
-#endif /* AMD_SABRINA_ACPI_H */
+#endif /* AMD_MENDOCINO_ACPI_H */

src/soc/amd/mendocino/include/soc/amd_pci_int_defs.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_AMD_PCI_INT_DEFS_H
+#ifndef AMD_MENDOCINO_AMD_PCI_INT_DEFS_H
-#define AMD_SABRINA_AMD_PCI_INT_DEFS_H
+#define AMD_MENDOCINO_AMD_PCI_INT_DEFS_H
 
 /*
  * PIRQ and device routing - these define the index into the
@@ -59,4 +59,4 @@
 #define PIRQ_UART2	0x78	/* UART2 */
 #define PIRQ_UART3	0x79	/* UART3 */
 
-#endif /* AMD_SABRINA_AMD_PCI_INT_DEFS_H */
+#endif /* AMD_MENDOCINO_AMD_PCI_INT_DEFS_H */

src/soc/amd/mendocino/include/soc/aoac_defs.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_AOAC_DEFS_H
+#ifndef AMD_MENDOCINO_AOAC_DEFS_H
-#define AMD_SABRINA_AOAC_DEFS_H
+#define AMD_MENDOCINO_AOAC_DEFS_H
 
 /* FCH AOAC device offsets for AOAC_DEV_D3_CTL/AOAC_DEV_D3_STATE */
 #define FCH_AOAC_DEV_CLK_GEN		0
@@ -20,4 +20,4 @@
 #define FCH_AOAC_DEV_ESPI		27
 #define FCH_AOAC_DEV_EMMC		28
 
-#endif /* AMD_SABRINA_AOAC_DEFS_H */
+#endif /* AMD_MENDOCINO_AOAC_DEFS_H */

src/soc/amd/mendocino/include/soc/cpu.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_MENDOCINO_CPU_H
+#define AMD_MENDOCINO_CPU_H
+
+#define MENDOCINO_A0_CPUID	0x008a0f00
+
+#endif /* AMD_MENDOCINO_CPU_H */

src/soc/amd/mendocino/include/soc/data_fabric.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_DATA_FABRIC_H
+#ifndef AMD_MENDOCINO_DATA_FABRIC_H
-#define AMD_SABRINA_DATA_FABRIC_H
+#define AMD_MENDOCINO_DATA_FABRIC_H
 
 #include <types.h>
 
@@ -14,4 +14,4 @@
 
 void data_fabric_set_mmio_np(void);
 
-#endif /* AMD_SABRINA_DATA_FABRIC_H */
+#endif /* AMD_MENDOCINO_DATA_FABRIC_H */

src/soc/amd/mendocino/include/soc/espi.h

@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_MENDOCINO_ESPI_H
+#define AMD_MENDOCINO_ESPI_H
+
+void espi_switch_to_spi1_pads(void);
+
+#endif /* AMD_MENDOCINO_ESPI_H */

src/soc/amd/mendocino/include/soc/gpio.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_GPIO_H
+#ifndef AMD_MENDOCINO_GPIO_H
-#define AMD_SABRINA_GPIO_H
+#define AMD_MENDOCINO_GPIO_H
 
 #define GPIO_DEVICE_NAME	"AMD0030"
 #define GPIO_DEVICE_DESC	"GPIO Controller"
@@ -321,4 +321,4 @@
 #define GPIO_157_IOMUX_GPIOxx 0
 #define GPIO_157_IOMUX_UART4_INTR 1
 
-#endif /* AMD_SABRINA_GPIO_H */
+#endif /* AMD_MENDOCINO_GPIO_H */

src/soc/amd/mendocino/include/soc/i2c.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_I2C_H
+#ifndef AMD_MENDOCINO_I2C_H
-#define AMD_SABRINA_I2C_H
+#define AMD_MENDOCINO_I2C_H
 
 #include <soc/gpio.h>
 #include <types.h>
@@ -25,4 +25,4 @@
 
 void i2c_set_bar(unsigned int bus, uintptr_t bar);
 
-#endif /* AMD_SABRINA_I2C_H */
+#endif /* AMD_MENDOCINO_I2C_H */

src/soc/amd/mendocino/include/soc/iomap.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_IOMAP_H
+#ifndef AMD_MENDOCINO_IOMAP_H
-#define AMD_SABRINA_IOMAP_H
+#define AMD_MENDOCINO_IOMAP_H
 
 #define I2C_MASTER_DEV_COUNT		4
 #define I2C_MASTER_START_INDEX		0
@@ -54,4 +54,4 @@
 #define   ACPI_GPE0_EN			(ACPI_GPE0_BLK + 0x04)
 #define SMB_BASE_ADDR			0x0b00
 
-#endif /* AMD_SABRINA_IOMAP_H */
+#endif /* AMD_MENDOCINO_IOMAP_H */

src/soc/amd/mendocino/include/soc/lpc.h

@@ -2,8 +2,8 @@
 
 /* TODO: Check if this is still correct */
 
-#ifndef AMD_SABRINA_LPC_H
+#ifndef AMD_MENDOCINO_LPC_H
-#define AMD_SABRINA_LPC_H
+#define AMD_MENDOCINO_LPC_H
 
 /* LPC_MISC_CONTROL_BITS at D14F3x078 */
 /* The definitions of bits 9 and 10 are swapped on Picasso and older compared to Renoir/Cezanne
@@ -21,4 +21,4 @@
 #define   SPI_ROM_ALT_ENABLE		BIT(0)
 #define   SPI_PRESERVE_BITS		(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4))
 
-#endif /* AMD_SABRINA_LPC_H */
+#endif /* AMD_MENDOCINO_LPC_H */

src/soc/amd/mendocino/include/soc/msr.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_MSR_H
+#ifndef AMD_MENDOCINO_MSR_H
-#define AMD_SABRINA_MSR_H
+#define AMD_MENDOCINO_MSR_H
 
 /* MSRC001_00[6B:64] P-state [7:0] bit definitions */
 #define PSTATE_DEF_HI_ENABLE_SHIFT	31
@@ -28,4 +28,4 @@
 #define MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe7
 #define MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT	0xe8
 
-#endif /* AMD_SABRINA_MSR_H */
+#endif /* AMD_MENDOCINO_MSR_H */

src/soc/amd/mendocino/include/soc/nvs.h

@@ -4,12 +4,12 @@
 
 /*
  * NOTE: The layout of the global_nvs structure below must match the layout
- * in soc/soc/amd/sabrina/acpi/globalnvs.asl !!!
+ * in soc/soc/amd/mendocino/acpi/globalnvs.asl !!!
  *
  */
 
-#ifndef AMD_SABRINA_NVS_H
+#ifndef AMD_MENDOCINO_NVS_H
-#define AMD_SABRINA_NVS_H
+#define AMD_MENDOCINO_NVS_H
 
 #include <stdint.h>
 
@@ -26,4 +26,4 @@ struct __packed global_nvs {
 	uint8_t		tpsv; /* 0x19 - Passive Threshold */
 };
 
-#endif /* AMD_SABRINA_NVS_H */
+#endif /* AMD_MENDOCINO_NVS_H */

src/soc/amd/mendocino/include/soc/pci_devs.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_PCI_DEVS_H
+#ifndef AMD_MENDOCINO_PCI_DEVS_H
-#define AMD_SABRINA_PCI_DEVS_H
+#define AMD_MENDOCINO_PCI_DEVS_H
 
 #include <device/pci_def.h>
 #include <amdblocks/pci_devs.h>
@@ -130,4 +130,4 @@
 #define DF_F7_DEVFN		PCI_DEVFN(DF_DEV, 7)
 #define SOC_DF_F7_DEV		_SOC_DEV(DF_DEV, 7)
 
-#endif /* AMD_SABRINA_PCI_DEVS_H */
+#endif /* AMD_MENDOCINO_PCI_DEVS_H */

src/soc/amd/mendocino/include/soc/platform_descriptors.h

@@ -2,8 +2,8 @@
 
 /* TODO: Check if this is still correct */
 
-#ifndef AMD_SABRINA_PLATFORM_DESCRIPTORS_H
+#ifndef AMD_MENDOCINO_PLATFORM_DESCRIPTORS_H
-#define AMD_SABRINA_PLATFORM_DESCRIPTORS_H
+#define AMD_MENDOCINO_PLATFORM_DESCRIPTORS_H
 
 #include <types.h>
 #include <platform_descriptors.h>
@@ -16,4 +16,4 @@ void mainboard_get_dxio_ddi_descriptors(
 
 void mb_pre_fspm(FSP_M_CONFIG *mcfg);
 
-#endif /* AMD_SABRINA_PLATFORM_DESCRIPTORS_H */
+#endif /* AMD_MENDOCINO_PLATFORM_DESCRIPTORS_H */

src/soc/amd/mendocino/include/soc/psp_transfer.h

@@ -2,8 +2,8 @@
 
 /* TODO: Check if this is still correct */
 
-#ifndef AMD_SABRINA_PSP_TRANSFER_H
+#ifndef AMD_MENDOCINO_PSP_TRANSFER_H
-#define AMD_SABRINA_PSP_TRANSFER_H
+#define AMD_MENDOCINO_PSP_TRANSFER_H
 
 # if (CONFIG_CMOS_RECOVERY_BYTE != 0)
 #  define CMOS_RECOVERY_BYTE CONFIG_CMOS_RECOVERY_BYTE
@@ -61,4 +61,4 @@ void replay_transfer_buffer_cbmemc(void);
 void boot_with_psp_timestamp(uint64_t base_timestamp);
 
 #endif
-#endif	/* AMD_SABRINA_PSP_TRANSFER_H */
+#endif	/* AMD_MENDOCINO_PSP_TRANSFER_H */

src/soc/amd/mendocino/include/soc/psp_verstage_addr.h

@@ -2,8 +2,8 @@
 
 /* TODO: Check if this is still correct */
 
-#ifndef AMD_SABRINA_PSP_VERSTAGE_ADDR_H
+#ifndef AMD_MENDOCINO_PSP_VERSTAGE_ADDR_H
-#define AMD_SABRINA_PSP_VERSTAGE_ADDR_H
+#define AMD_MENDOCINO_PSP_VERSTAGE_ADDR_H
 
 /*
  * Start of available space is 0x0 and this is where the
@@ -22,4 +22,4 @@
 #define PSP_VERSTAGE_STACK_START	0x2a000
 #define PSP_VERSTAGE_STACK_SIZE		(40K)
 
-#endif  /* AMD_SABRINA_PSP_VERSTAGE_ADDR_H */
+#endif  /* AMD_MENDOCINO_PSP_VERSTAGE_ADDR_H */

src/soc/amd/mendocino/include/soc/smi.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#ifndef AMD_SABRINA_SMI_H
+#ifndef AMD_MENDOCINO_SMI_H
-#define AMD_SABRINA_SMI_H
+#define AMD_MENDOCINO_SMI_H
 
 #include <types.h>
 
@@ -186,4 +186,4 @@
 
 #define SMI_MODE_MASK			0x03
 
-#endif /* AMD_SABRINA_SMI_H */
+#endif /* AMD_MENDOCINO_SMI_H */

src/soc/amd/mendocino/include/soc/smu.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_SMU_H
+#ifndef AMD_MENDOCINO_SMU_H
-#define AMD_SABRINA_SMU_H
+#define AMD_MENDOCINO_SMU_H
 
 /* SMU mailbox register offsets in SMN */
 #define SMN_SMU_MESG_ID		0x3b10528
@@ -20,4 +20,4 @@ enum smu_message_id {
  */
 void smu_sx_entry(void);
 
-#endif /* AMD_SABRINA_SMU_H */
+#endif /* AMD_MENDOCINO_SMU_H */

src/soc/amd/mendocino/include/soc/southbridge.h

@@ -2,8 +2,8 @@
 
 /* TODO: Check if this is still correct */
 
-#ifndef AMD_SABRINA_SOUTHBRIDGE_H
+#ifndef AMD_MENDOCINO_SOUTHBRIDGE_H
-#define AMD_SABRINA_SOUTHBRIDGE_H
+#define AMD_MENDOCINO_SOUTHBRIDGE_H
 
 #include <soc/iomap.h>
 
@@ -124,4 +124,4 @@ void fch_final(void *chip_info);
 void enable_aoac_devices(void);
 void wait_for_aoac_enabled(unsigned int dev);
 
-#endif /* AMD_SABRINA_SOUTHBRIDGE_H */
+#endif /* AMD_MENDOCINO_SOUTHBRIDGE_H */

src/soc/amd/mendocino/include/soc/uart.h

@@ -1,11 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#ifndef AMD_SABRINA_UART_H
+#ifndef AMD_MENDOCINO_UART_H
-#define AMD_SABRINA_UART_H
+#define AMD_MENDOCINO_UART_H
 
 #include <types.h>
 
 void set_uart_config(unsigned int idx); /* configure hardware of FCH UART selected by idx */
 void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */
 
-#endif /* AMD_SABRINA_UART_H */
+#endif /* AMD_MENDOCINO_UART_H */

src/soc/amd/mendocino/psp_verstage/Makefile.inc

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+# TODO(b/239090306): Check if this is still correct
+
+verstage-generic-ccopts += -I$(src)/soc/amd/mendocino/psp_verstage/include
+verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/mendocino/include
+
+verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
+
+subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage
+
+verstage-y += svc.c
+verstage-y += chipset.c
+verstage-y += uart.c
+
+verstage-y += $(top)/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_startup.S
+verstage-y += $(top)/src/vendorcode/amd/fsp/mendocino/bl_uapp/bl_uapp_end.S

src/soc/amd/mendocino/root_complex.c

@@ -186,7 +186,7 @@ static void root_complex_init(struct device *dev)
 
 static void acipgen_dptci(void)
 {
-	const struct soc_amd_sabrina_config *config = config_of_soc();
+	const struct soc_amd_mendocino_config *config = config_of_soc();
 
 	if (!config->dptc_enable)
 		return;

src/soc/amd/mendocino/uart.c

@@ -117,7 +117,7 @@ static void uart_read_resources(struct device *dev)
 	mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4);
 }
 
-struct device_operations sabrina_uart_mmio_ops = {
+struct device_operations mendocino_uart_mmio_ops = {
 	.read_resources = uart_read_resources,
 	.set_resources = noop_set_resources,
 	.scan_bus = scan_static_bus,

src/soc/amd/sabrina/include/soc/cpu.h

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_SABRINA_CPU_H
-#define AMD_SABRINA_CPU_H
-
-#define SABRINA_A0_CPUID	0x008a0f00
-
-#endif /* AMD_SABRINA_CPU_H */

src/soc/amd/sabrina/include/soc/espi.h

@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_SABRINA_ESPI_H
-#define AMD_SABRINA_ESPI_H
-
-void espi_switch_to_spi1_pads(void);
-
-#endif /* AMD_SABRINA_ESPI_H */

src/soc/amd/sabrina/psp_verstage/Makefile.inc

@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-# TODO: Check if this is still correct
-
-verstage-generic-ccopts += -I$(src)/soc/amd/sabrina/psp_verstage/include
-verstage-generic-ccopts += -I$(src)/vendorcode/amd/fsp/sabrina/include
-
-verstage-generic-ccopts += -I$(src)/soc/amd/common/psp_verstage/include
-
-subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += ../../common/psp_verstage
-
-verstage-y += svc.c
-verstage-y += chipset.c
-verstage-y += uart.c
-
-verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_startup.S
-verstage-y += $(top)/src/vendorcode/amd/fsp/sabrina/bl_uapp/bl_uapp_end.S

src/vendorcode/amd/fsp/mendocino/platform_descriptors.h

@@ -160,11 +160,11 @@ typedef struct __packed {
 } fsp_ddi_descriptor;
 
 /*
- * Sabrina DXIO Descriptor: Used for assigning lanes to PCIe engines, configure
+ * Mendocino DXIO Descriptor: Used for assigning lanes to PCIe engines, configure
  * bifurcation and other settings. Beware that the lane numbers in here are the
  * logical and not the physical lane numbers!
  *
- * Sabrina DXIO logical lane to physical PCIe lane mapping:
+ * Mendocino DXIO logical lane to physical PCIe lane mapping:
  *
  * logical | physical
  * --------|------------