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cpu/intel/core2: Cache XIP romstage with C_ENVIRONMENT_BOOTBLOCK. 

Tested on Thinkpad X200: the romstage execution speeds are back to
pre-C_ENVIRONMENT_BOOTBLOCK levels.

Change-Id: Id0b50d2f56e7cc0e055cdc8b9aa28794327eca28
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35994
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-10-12 17:55:49 +02:00 committed by Nico Huber
parent 47be2d9f70
commit 4f7568b126
2 changed files with 2 additions and 0 deletions
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1
src/cpu/intel/model_1067x/Kconfig
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@ -13,3 +13,4 @@ config CPU_INTEL_MODEL_1067X
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK

1
src/cpu/intel/model_6fx/Kconfig
View File

@ -14,3 +14,4 @@ config CPU_INTEL_MODEL_6FX
select SUPPORT_CPU_UCODE_IN_CBFS
select CPU_INTEL_COMMON
select CPU_INTEL_COMMON_TIMEBASE
select SETUP_XIP_CACHE if C_ENVIRONMENT_BOOTBLOCK