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fox_wtm2: First step support for coreboot-based graphics startup 

This code is the initial version of FUI for haswell and wtm2.

The code is simplified from before in many ways. I've gotten rid of
the opcode table, because it obscured meaning and I don't think it is
needed any more. Register sets, mainly used for reset, are just lines
of code -- not many of them. There are a bunch of not-yet-documented
registers here; the VBIOS seemed to think they were necessary and
testing shows they seem to be right.

As a bit of added paranoia, we always include the VBIOS code as our
emergency recovery path. You have to run it now anyways, so this is no
regression from our current situation; and, if all goes well, in a
week (or so), you'll never have to run it again, but like the Force
and nose hair, it will be with you always.

The code can return in three ways. The first, best way is success:
panel is up and the VBIOS need not run. The second mode is that we
tried to light up the panel but could not, for some reason, but will
return with the panel partly up. In this case, it's ok not to power
cycle the panel. The third, worst case, which will NEVER happen, ha
ha, is that we have to turn the panel off and wait the required 600ms
for it to cycle. Life sucks sometimes. This failure mode is in the
'hang on we're going to fix it' category now that we have ramstage in
RW.

The Big Goal here is to create something other coreboot ports can use
as well. The guys doing the x60 report that the link FUI works,
without too many mods, on that chipset, so it seems Intel is keeping
things from changing too much over time.

Also, again, please note: this and the next 3 versions will ALWAYS fail.
The goal is to verify the correctness of the recovery path.

The bizarre tab-space formatting in drm_dp_helper.h is from the original,
as in i915_reg.h

Change-Id: I6ecf454633029d185c29d470980b5a0f3114a8ce
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Ronald G. Minnich 2013-04-17 16:57:30 -07:00 committed by Stefan Reinauer
parent 2a66d6b804
commit 4f78b18749
9 changed files with 232 additions and 7872 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mainboard/intel/wtm2/Makefile.inc
View File

@ -20,7 +20,7 @@
romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += i915io.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += graphics.c
ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c

89
src/mainboard/intel/wtm2/graphics.c Normal file
View File

@ -0,0 +1,89 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/* this file was for the most part machine generated, and in future
* will be all machine generated. Avoid editing.
*/
#include <console/console.h>
#include "i915io.h"
void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
{
io_i915_write32(0x80000000,0x45400);
io_i915_write32(0x00000000,_CURACNTR);
io_i915_write32((/* PIPEA */0x0<<24)|0x00000000,_DSPACNTR);
io_i915_write32(0x00000000,_DSPBCNTR);
io_i915_write32(0x80000000,CPU_VGACNTRL);
io_i915_write32(0x00000000,_DSPASIZE+0xc);
io_i915_write32(0x00000000,_DSPBSURF);
io_i915_write32(0x00000000,0x4f050);
io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT |
DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 |
DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE |
DP_SYNC_VS_HIGH |0x00000091,DP_A);
io_i915_write32(0x00200090,_FDI_RXA_MISC);
io_i915_write32(0x0a000000,_FDI_RXA_MISC);
/* not yet documented anywhere that we can find. */
io_i915_write32(0x00000070,0x46408);
io_i915_write32(0x04000000,0x42090);
io_i915_write32(0x40000000,0x4f050);
io_i915_write32(0x00000000,0x9840);
io_i915_write32(0xa4000000,0x42090);
io_i915_write32(0x00004000,0x42080);
io_i915_write32(0x00ffffff,0x64f80);
io_i915_write32(0x0007000e,0x64f84);
io_i915_write32(0x00d75fff,0x64f88);
io_i915_write32(0x000f000a,0x64f8c);
io_i915_write32(0x00c30fff,0x64f90);
io_i915_write32(0x00060006,0x64f94);
io_i915_write32(0x00aaafff,0x64f98);
io_i915_write32(0x001e0000,0x64f9c);
io_i915_write32(0x00ffffff,0x64fa0);
io_i915_write32(0x000f000a,0x64fa4);
io_i915_write32(0x00d75fff,0x64fa8);
io_i915_write32(0x00160004,0x64fac);
io_i915_write32(0x00c30fff,0x64fb0);
io_i915_write32(0x001e0000,0x64fb4);
io_i915_write32(0x00ffffff,0x64fb8);
io_i915_write32(0x00060006,0x64fbc);
io_i915_write32(0x00d75fff,0x64fc0);
io_i915_write32(0x001e0000,0x64fc4);
io_i915_write32(0x00ffffff,0x64e00);
io_i915_write32(0x0006000e,0x64e04);
io_i915_write32(0x00d75fff,0x64e08);
io_i915_write32(0x0005000a,0x64e0c);
io_i915_write32(0x00c30fff,0x64e10);
io_i915_write32(0x00040006,0x64e14);
io_i915_write32(0x80aaafff,0x64e18);
io_i915_write32(0x000b0000,0x64e1c);
io_i915_write32(0x00ffffff,0x64e20);
io_i915_write32(0x0005000a,0x64e24);
io_i915_write32(0x00d75fff,0x64e28);
io_i915_write32(0x000c0004,0x64e2c);
io_i915_write32(0x80c30fff,0x64e30);
io_i915_write32(0x000b0000,0x64e34);
io_i915_write32(0x00ffffff,0x64e38);
io_i915_write32(0x00040006,0x64e3c);
io_i915_write32(0x80d75fff,0x64e40);
io_i915_write32(0x000b0000,0x64e44);
/* end not yet documented. */
io_i915_write32(0x10000000,SDEISR+0x30);
}

337
src/mainboard/intel/wtm2/i915.c
View File

@ -30,7 +30,7 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <arch/io.h> #include <arch/io.h>
#include <arch/interrupt.h> #include <arch/interrupt.h>
#include <arch/coreboot_tables.h> #include <boot/coreboot_tables.h>
#include "hda_verb.h" #include "hda_verb.h"
#include <smbios.h> #include <smbios.h>
#include <device/pci.h> #include <device/pci.h>
@ -40,15 +40,10 @@
#include <cpu/x86/tsc.h> #include <cpu/x86/tsc.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <edid.h> #include <edid.h>
#include "i915io.h" #include "i915io.h"
enum {
vmsg = 1, vio = 2, vspin = 4,
};
static int verbose = 0; static int verbose = 0;
static unsigned int *mmio; static unsigned int *mmio;
@ -57,7 +52,6 @@ static unsigned short addrport;
static unsigned short dataport; static unsigned short dataport;
static unsigned int physbase; static unsigned int physbase;
extern int oprom_is_loaded; extern int oprom_is_loaded;
static u32 htotal, hblank, hsync, vtotal, vblank, vsync;
const u32 link_edid_data[] = { const u32 link_edid_data[] = {
0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000, 0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000,
@ -70,8 +64,7 @@ const u32 link_edid_data[] = {
0x31504c00, 0x45513932, 0x50532d31, 0x24003141, 0x31504c00, 0x45513932, 0x50532d31, 0x24003141,
}; };
#define READ32(addr) io_i915_READ32(addr) static int ioread = 0, iowrite = 0;
#define WRITE32(val, addr) io_i915_WRITE32(val, addr)
static char *regname(unsigned long addr) static char *regname(unsigned long addr)
{ {
@ -80,36 +73,43 @@ static char *regname(unsigned long addr)
return name; return name;
} }
unsigned long io_i915_READ32(unsigned long addr) unsigned long io_i915_read32(unsigned long addr)
{ {
unsigned long val; unsigned long val;
outl(addr, addrport); outl(addr, addrport);
val = inl(dataport); val = inl(dataport);
ioread += 2;
if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val); if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val);
return val; return val;
} }
void io_i915_WRITE32(unsigned long val, unsigned long addr) void io_i915_write32(unsigned long val, unsigned long addr)
{ {
if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val); if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val);
outl(addr, addrport); outl(addr, addrport);
outl(val, dataport); outl(val, dataport);
iowrite += 2;
} }
/* GTT is the Global Translation Table for the graphics pipeline.
/* * It is used to translate graphics addresses to physical
2560 * memory addresses. As in the CPU, GTTs map 4K pages.
4 words per * The setgtt function adds a further bit of flexibility:
4 *p * it allows you to set a range (the first two parameters) to point
10240 * to a physical address (third parameter);the physical address is
4k bytes per page * incremented by a count (fourth parameter) for each GTT in the
4096/p * range.
2.50 * Why do it this way? For ultrafast startup,
1700 lines * we can point all the GTT entries to point to one page,
1700 * p * and set that page to 0s:
4250.00 * memset(physbase, 0, 4096);
PTEs * setgtt(0, 4250, physbase, 0);
* this takes about 2 ms, and is a win because zeroing
* the page takes a up to 200 ms.
* This call sets the GTT to point to a linear range of pages
* starting at physbase.
*/ */
static void static void
setgtt(int start, int end, unsigned long base, int inc) setgtt(int start, int end, unsigned long base, int inc)
{ {
@ -117,7 +117,7 @@ setgtt(int start, int end, unsigned long base, int inc)
for(i = start; i < end; i++){ for(i = start; i < end; i++){
u32 word = base + i*inc; u32 word = base + i*inc;
WRITE32(word|1,(i*4)|1); io_i915_write32(word|1,(i*4)|1);
} }
} }
@ -137,36 +137,29 @@ static unsigned long globalmicroseconds(void)
return microseconds(globalstart, rdtscll()); return microseconds(globalstart, rdtscll());
} }
extern struct iodef iodefs[];
extern int niodefs;
static int i915_init_done = 0; static int i915_init_done = 0;
/* fill the palette. This runs when the P opcode is hit. */
static void palette(void)
{
int i;
unsigned long color = 0;
for(i = 0; i < 256; i++, color += 0x010101){
io_i915_WRITE32(color, _LGC_PALETTE_A + (i<<2));
}
}
int vbe_mode_info_valid(void);
int vbe_mode_info_valid(void) int vbe_mode_info_valid(void)
{ {
return i915_init_done; return i915_init_done;
} }
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer) void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
{ {
printk(BIOS_SPEW, "fill_lb_framebuffer: graphics is %p\n", (void *)graphics); printk(BIOS_SPEW, "fill_lb_framebuffer: graphics is %p\n",
(void *)graphics);
/* Please note: these will be filled from EDID.
* these values are a placeholder.
*/
framebuffer->physical_address = graphics; framebuffer->physical_address = graphics;
framebuffer->x_resolution = 2560; /* these are a fantasy, but will be fixed once we're getting
* info from the hardware. Hard to get from the device tree,
* which is arguably a defect of the device tree. Bear with me,
* this Will Get Fixed.
*/
framebuffer->x_resolution = 1960;
framebuffer->y_resolution = 1700; framebuffer->y_resolution = 1700;
framebuffer->bytes_per_line = 10240; framebuffer->bytes_per_line = 1960*4;
framebuffer->bits_per_pixel = 32; framebuffer->bits_per_pixel = 32;
framebuffer->red_mask_pos = 16; framebuffer->red_mask_pos = 16;
framebuffer->red_mask_size = 8; framebuffer->red_mask_size = 8;
@ -179,94 +172,21 @@ void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
} }
static unsigned long times[4096]; int i915lightup(unsigned int physbase,
unsigned int iobase,
static int run(int index) unsigned int mmio,
{
int i, prev = 0;
struct iodef *id, *lastidread = 0;
unsigned long u, t;
if (index >= niodefs)
return index;
/* state machine! */
for(i = index, id = &iodefs[i]; id->op; i++, id++){
switch(id->op){
case M:
if (verbose & vmsg) printk(BIOS_SPEW, "%ld: %s\n",
globalmicroseconds(), id->msg);
break;
case P:
palette();
break;
case R:
u = READ32(id->addr);
if (verbose & vio)
printk(BIOS_SPEW, "\texpect %08lx\n", id->data);
/* we're looking for something. */
if (lastidread->addr == id->addr){
/* they're going to be polling.
* just do it 1000 times
*/
for(t = 0; t < 1000 && id->data != u; t++){
u = READ32(id->addr);
}
if (verbose & vspin) printk(BIOS_SPEW,
"%s: # loops %ld got %08lx want %08lx\n",
regname(id->addr),
t, u, id->data);
}
lastidread = id;
break;
case W:
WRITE32(id->data, id->addr);
if (id->addr == PCH_PP_CONTROL){
if (verbose & vio)
printk(BIOS_SPEW, "PCH_PP_CONTROL\n");
switch(id->data & 0xf){
case 8: break;
case 7: break;
default: udelay(100000);
if (verbose & vio)
printk(BIOS_SPEW, "U %d\n", 100000);
}
}
break;
case V:
if (id->count < 8){
prev = verbose;
verbose = id->count;
} else {
verbose = prev;
}
printk(BIOS_SPEW, "Change verbosity to %d\n", verbose);
break;
case I:
printk(BIOS_SPEW, "run: return %d\n", i+1);
return i+1;
break;
default:
printk(BIOS_SPEW, "BAD TABLE, opcode %d @ %d\n", id->op, i);
return -1;
}
if (id->udelay)
udelay(id->udelay);
if (i < ARRAY_SIZE(times))
times[i] = globalmicroseconds();
}
printk(BIOS_SPEW, "run: return %d\n", i);
return i+1;
}
int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
unsigned int gfx); unsigned int gfx);
int i915lightup(unsigned int pphysbase, unsigned int piobase, int i915lightup(unsigned int pphysbase, unsigned int piobase,
unsigned int pmmio, unsigned int pgfx) unsigned int pmmio, unsigned int pgfx)
{ {
static struct edid edid; int must_cycle_power = 0;
/* frame buffer pointer */
u32 *l;
int i;
unsigned long before_gtt, after_gtt;
int index;
u32 auxin[16], auxout[16];
mmio = (void *)pmmio; mmio = (void *)pmmio;
addrport = piobase; addrport = piobase;
dataport = addrport + 4; dataport = addrport + 4;
@ -278,128 +198,55 @@ int i915lightup(unsigned int pphysbase, unsigned int piobase,
(void *)graphics, mmio, addrport, physbase); (void *)graphics, mmio, addrport, physbase);
globalstart = rdtscll(); globalstart = rdtscll();
/* turn it on. The VBIOS does it this way, so we hope that's ok. */
index = run(0);
if (0){
decode_edid((unsigned char *)&link_edid_data, sizeof(link_edid_data), &edid);
htotal = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
hblank = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HBLANK(pipe),0x%08x)\n", hblank);
hsync = (edid.ha + edid.hso - 1) |
((edid.ha + edid.hso + edid.hspw- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HSYNC(pipe),0x%08x)\n", hsync);
vtotal = (edid.va - 1) | ((edid.va + edid.vbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VTOTAL(pipe), %08x)\n", vtotal);
vblank = (edid.va - 1) | ((edid.va + edid.vbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VBLANK(pipe),0x%08x)\n", vblank);
vsync = (edid.va + edid.vso - 1) |((edid.va + edid.vso + edid.vspw- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(VSYNC(pipe),0x%08x)\n", vsync);
printk(BIOS_SPEW, "Table has %d elements\n", niodefs);
index = run(0);
printk(BIOS_SPEW, "Run returns %d\n", index);
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_DPCD_REV<<8|0xe;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 14);
auxout[0] = 0<<31 /* i2c */|1<<30|0x0<<28/*W*/|0x0<<8|0x0;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
index = run(index);
printk(BIOS_SPEW, "Run returns %d\n", index);
auxout[0] = 0<<31 /* i2c */|0<<30|0x0<<28/*W*/|0x0<<8|0x0;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 3, auxin, 0);
index = run(index);
printk(BIOS_SPEW, "Run returns %d\n", index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_SET_POWER<<8|0x0;
auxout[1] = 0x01000000;
/* DP_SET_POWER_D0 | DP_PSR_SINK_INACTIVE |
* (0x0<<13602104)|0x00000001*/ /* broken, fix. */
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_LINK_BW_SET<<8|0x8;
auxout[1] = 0x0a840000;
/*( DP_LINK_BW_2_7 &0xa)|0x0000840a*/
auxout[2] = 0x00000000;
auxout[3] = 0x01000000;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 13, auxin, 0);
index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0;
auxout[1] = 0x21000000;
/* DP_TRAINING_PATTERN_1 | DP_LINK_SCRAMBLING_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000021*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3;
auxout[1] = 0x00000000;
/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
index = run(index);
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0;
auxout[1] = 0x22000000;
/* DP_TRAINING_PATTERN_2 | DP_LINK_SCRAMBLING_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000022*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_LANE0_SET<<8|0x3;
auxout[1] = 0x00000000;
/* DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0 |0x00000000*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 8, auxin, 0);
index = run(index);
auxout[0] = 1<<31 /* dp */|0x1<<28/*R*/|DP_LANE0_1_STATUS<<8|0x5;
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 4, auxin, 5);
index = run(index);
auxout[0] = 1<<31 /* dp */|0x0<<28/*W*/|DP_TRAINING_PATTERN_SET<<8|0x0;
auxout[1] = 0x00000000;
/* DP_TRAINING_PATTERN_DISABLE | DP_LINK_QUAL_PATTERN_DISABLE |
* DP_SYMBOL_ERROR_COUNT_BOTH |0x00000000*/
intel_dp_aux_ch(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, auxout, 5, auxin, 0);
index = run(index);
}
if (index != niodefs)
printk(BIOS_ERR, "Left over IO work in i915_lightup"
" -- this is likely a table error. "
"Only %d of %d were done.\n", index, niodefs);
printk(BIOS_SPEW, "DONE startup\n");
verbose = 0; verbose = 0;
/* GTT is the Global Translation Table for the graphics pipeline. io_i915_write32(0xabcd000f, PCH_PP_CONTROL);
* It is used to translate graphics addresses to physical
* memory addresses. As in the CPU, GTTs map 4K pages. /* the AUX channel needs a small amount of time to spin up.
* There are 32 bits per pixel, or 4 bytes, * Rather than udelay, do some useful work:
* which means 1024 pixels per page. * Zero out the frame buffer memory,
* There are 4250 GTTs on Link: * and set the global translation table (GTT)
* 2650 (X) * 1700 (Y) pixels / 1024 pixels per page.
* The setgtt function adds a further bit of flexibility:
* it allows you to set a range (the first two parameters) to point
* to a physical address (third parameter);the physical address is
* incremented by a count (fourth parameter) for each GTT in the
* range.
* Why do it this way? For ultrafast startup,
* we can point all the GTT entries to point to one page,
* and set that page to 0s:
* memset(physbase, 0, 4096);
* setgtt(0, 4250, physbase, 0);
* this takes about 2 ms, and is a win because zeroing
* the page takes a up to 200 ms. We will be exploiting this
* trick in a later rev of this code.
* This call sets the GTT to point to a linear range of pages
* starting at physbase.
*/ */
printk(BIOS_SPEW, "Set not-White (%08x) for %d pixels\n", 0xffffff,
FRAME_BUFFER_BYTES/sizeof(u32));
for(l = (u32 *)graphics, i = 0;
i < FRAME_BUFFER_BYTES/sizeof(u32); i++){
l[i] = 0x1122ff;
}
printk(BIOS_SPEW, "GTT: set %d pages starting at %p\n",
FRAME_BUFFER_PAGES, (void *)physbase);
before_gtt = globalmicroseconds();
setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096); setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
printk(BIOS_SPEW, "memset %p to 0 for %d bytes\n", after_gtt = globalmicroseconds();
(void *)graphics, FRAME_BUFFER_BYTES);
memset((void *)graphics, 0, FRAME_BUFFER_BYTES); /* The reset is basically harmless, and can be
printk(BIOS_SPEW, "%ld microseconds\n", globalmicroseconds()); * repeated by the VBIOS in any event.
*/
graphics_register_reset(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, verbose);
/* failures after this point can return without
* powering off the panel.
*/
if (1)
goto fail;
/* failures after this point MUST power off the panel
* and wait 600 ms.
*/
i915_init_done = 1; i915_init_done = 1;
oprom_is_loaded = 1; oprom_is_loaded = 1;
return 0; return 1;
fail:
printk(BIOS_SPEW, "Graphics could not be started;");
if (must_cycle_power){
printk(BIOS_SPEW, "Turn off power and wait ...");
io_i915_write32(0xabcd0000, PCH_PP_CONTROL);
udelay(600000);
}
printk(BIOS_SPEW, "Returning.\n");
return 0;
} }

7563
src/mainboard/intel/wtm2/i915io.c
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File diff suppressed because it is too large Load Diff

86
src/mainboard/intel/wtm2/i915io.h
View File

@ -18,71 +18,59 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include "i915_reg.h" #include <northbridge/intel/haswell/i915_reg.h>
#include "drm_dp_helper.h" #include <northbridge/intel/haswell/drm_dp_helper.h>
/* things that are, strangely, not defined anywhere? */ /* things that are, strangely, not defined anywhere? */
#define PCH_PP_UNLOCK 0xabcd0000 #define PCH_PP_UNLOCK 0xabcd0000
#define WMx_LP_SR_EN (1<<31) #define WMx_LP_SR_EN (1<<31)
#define PRB0_TAIL 0x02030
#define PRB0_HEAD 0x02034
#define PRB0_START 0x02038
#define PRB0_CTL 0x0203c
/* Google Link-specific defines */
/* mainboard-specific defines */
/* how many bytes do we need for the framebuffer?
* Well, this gets messy. To get an exact answer, we have
* to ask the panel, but we'd rather zero the memory
* and set up the gtt while the panel powers up. So,
* we take a reasonable guess, secure in the knowledge that the
* MRC has to overestimate the number of bytes used.
* 8 MiB is a very safe guess. There may be a better way later, but
* fact is, the initial framebuffer is only very temporary. And taking
* a little long is ok; this is done much faster than the AUX
* channel is ready for IO.
*/
#define FRAME_BUFFER_BYTES (8*MiB)
/* how many 4096-byte pages do we need for the framebuffer? /* how many 4096-byte pages do we need for the framebuffer?
* There are 32 bits per pixel, or 4 bytes, * There are hard ways to get this, and easy ways:
* which means 1024 pixels per page. * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
* HencetThere are 4250 GTTs on Link: * on this chip.
* 2650 (X) * 1700 (Y) pixels / 1024 pixels per page.
*/ */
#define FRAME_BUFFER_PAGES ((2560*1700)/1024) #define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
#define FRAME_BUFFER_BYTES (FRAME_BUFFER_PAGES*4096)
/* One-letter commands for code not mean to be ready for humans.
* The code was generated by a set of programs/scripts. /* debug enums. These are for printks that, due to their place in the
* M print out a kernel message * middle of graphics device IO, might change timing. Use with care
* R read a register. We do these mainly to ensure that if hardware wanted * or not at all.
* the register read, it was read; also, in debug, we can see what was expected
* and what was found. This has proven *very* useful to get this debugged.
* The udelay, if non-zero, will make sure there is a
* udelay() call with the value.
* The count is from the kernel and tells us how many times this read was done.
* Also useful for debugging and the state
* machine uses the info to drive a poll.
* W Write a register
* V set verbosity. It's a bit mask.
* 0 -> nothing
* 1 -> print kernel messages
* 2 -> print IO ops
* 4 -> print the number of times we spin on a register in a poll
* 8 -> restore whatever the previous verbosity level was
* (only one deep stack)
*
* Again, this is not really meant for human consumption. There is not a poll
* operator as such because, sometimes, there is a read/write/read where the
* second read is a poll, and this chipset is so touchy I'm reluctant to move
* things around and/or delete too many reads.
*/ */
#define M 1 enum {
#define R 2 vio = 2, /* dump every IO */
#define W 4 vspin = 4, /* print # of times we spun on a register value */
#define V 8
#define I 16
#define P 32
struct iodef {
unsigned char op;
unsigned int count;
const char *msg;
unsigned long addr;
unsigned long data;
unsigned long udelay;
}; };
/* i915.c */ /* i915.c */
unsigned long io_i915_READ32(unsigned long addr); unsigned long io_i915_READ32(unsigned long addr);
void io_i915_WRITE32(unsigned long val, unsigned long addr); void io_i915_WRITE32(unsigned long val, unsigned long addr);
int vbe_mode_info_valid(void);
void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
/* intel_dp.c */ /* intel_dp.c */
u32 pack_aux(u32 *src, int src_bytes); u32 pack_aux(u32 *src, int src_bytes);
void unpack_aux(u32 src, u32 *dst, int dst_bytes); void unpack_aux(u32 src, u8 *dst, int dst_bytes);
int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, int intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
u32 *recv, int recv_size); u8 *recv, int recv_size);
/* i915io.c */
void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose);

5
src/mainboard/intel/wtm2/intel_dp.c
View File

@ -47,9 +47,8 @@ pack_aux(u32 *src32, int src_bytes)
} }
void void
unpack_aux(u32 src, u32 *dst32, int dst_bytes) unpack_aux(u32 src, u8 *dst, int dst_bytes)
{ {
u8 *dst = (u8 *)dst32;
int i; int i;
if (dst_bytes > 4) if (dst_bytes > 4)
@ -60,7 +59,7 @@ unpack_aux(u32 src, u32 *dst32, int dst_bytes)
int int
intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes, intel_dp_aux_ch(u32 ch_ctl, u32 ch_data, u32 *send, int send_bytes,
u32 *recv, int recv_size) u8 *recv, int recv_size)
{ {
int i; int i;
int recv_bytes; int recv_bytes;

0
src/mainboard/intel/wtm2/drm_dp_helper.h → src/northbridge/intel/haswell/drm_dp_helper.h
View File

20
src/northbridge/intel/haswell/gma.c
View File

@ -1,7 +1,7 @@
/* /*
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2011 Chromium OS Authors * Copyright 2012 Google Inc.
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@ -189,6 +189,7 @@ static void gma_pm_init_post_vbios(struct device *dev)
static void gma_func0_init(struct device *dev) static void gma_func0_init(struct device *dev)
{ {
int lightup_ok = 0;
u32 reg32; u32 reg32;
u32 graphics_base; //, graphics_size; u32 graphics_base; //, graphics_size;
/* IGD needs to be Bus Master */ /* IGD needs to be Bus Master */
@ -205,14 +206,6 @@ static void gma_func0_init(struct device *dev)
/* Init graphics power management */ /* Init graphics power management */
gma_pm_init_pre_vbios(dev); gma_pm_init_pre_vbios(dev);
/* PCI Init, will run VBIOS */
#if !CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
printk(BIOS_SPEW, "Run the VBIOS init\n");
pci_dev_init(dev);
#endif
/* Post VBIOS init */
gma_pm_init_post_vbios(dev);
#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT #if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
printk(BIOS_SPEW, "NATIVE graphics, run native enable\n"); printk(BIOS_SPEW, "NATIVE graphics, run native enable\n");
u32 iobase, mmiobase, physbase; u32 iobase, mmiobase, physbase;
@ -221,8 +214,15 @@ static void gma_func0_init(struct device *dev)
physbase = pci_read_config32(dev, 0x5c) & ~0xf; physbase = pci_read_config32(dev, 0x5c) & ~0xf;
int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx); int i915lightup(u32 physbase, u32 iobase, u32 mmiobase, u32 gfx);
i915lightup(physbase, iobase, mmiobase, graphics_base); lightup_ok = i915lightup(physbase, iobase, mmiobase, graphics_base);
#endif #endif
if (! lightup_ok) {
printk(BIOS_SPEW, "FUI did not run; using VBIOS\n");
pci_dev_init(dev);
}
/* Post VBIOS init */
gma_pm_init_post_vbios(dev);
} }
static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)

0
src/mainboard/intel/wtm2/i915_reg.h → src/northbridge/intel/haswell/i915_reg.h
View File