arm64: exception handler registration
In order to build upon the arm64 exception handlers need to be registered. This provides very basic support to register a handler for a specific exception vector. BUG=chrome-os-partner:30785 BRANCH=None TEST=Built and booted into kernel. Change-Id: If046f0736765a2efeb23201c1d2d1f7f7db47dd2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a82e5e8d5900ebef16abdb68701be6beeb9ca13a Original-Change-Id: I0f68a48101ff48d582f5422871b9e7e5164357e4 Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/218650 Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/9088 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin
Patrick Georgi
parent
da1a0778ab
commit
4f89d97c06
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@ -29,56 +29,30 @@
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#include <stdint.h>
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#include <types.h>
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#include <arch/barrier.h>
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#include <arch/cache.h>
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#include <arch/exception.h>
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#include <arch/transition.h>
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#include <console/console.h>
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#include <arch/lib_helpers.h>
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static unsigned int test_exc;
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struct exception_handler_info
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{
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const char *name;
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};
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enum {
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EXC_SYNC_SP0 = 0,
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EXC_IRQ_SP0,
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EXC_FIQ_SP0,
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EXC_SERROR_SP0,
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EXC_SYNC_SP3,
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EXC_IRQ_SP3,
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EXC_FIQ_SP3,
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EXC_SERROR_SP3,
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EXC_SYNC_ELX_64,
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EXC_IRQ_ELX_64,
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EXC_FIQ_ELX_64,
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EXC_SERROR_ELX_64,
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EXC_SYNC_ELX_32,
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EXC_IRQ_ELX_32,
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EXC_FIQ_ELX_32,
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EXC_SERROR_ELX_32,
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EXC_COUNT
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};
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static struct exception_handler_info exceptions[EXC_COUNT] = {
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[EXC_SYNC_SP0] = { "_sync_sp_el0" },
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[EXC_IRQ_SP0] = { "_irq_sp_el0" },
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[EXC_FIQ_SP0] = { "_fiq_sp_el0" },
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[EXC_SERROR_SP0] = {"_serror_sp_el0"},
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[EXC_SYNC_SP3] = { "_sync_sp_el3" },
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[EXC_IRQ_SP3] = { "_irq_sp_el3" },
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[EXC_FIQ_SP3] = { "_fiq_sp_el3" },
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[EXC_SERROR_SP3] = {"_serror_sp_el3"},
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[EXC_SYNC_ELX_64] = { "_sync_elx_64" },
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[EXC_IRQ_ELX_64] = { "_irq_elx_64" },
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[EXC_FIQ_ELX_64] = { "_fiq_elx_64" },
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[EXC_SERROR_ELX_64] = {"_serror_elx_64"},
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[EXC_SYNC_ELX_32] = { "_sync_elx_32" },
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[EXC_IRQ_ELX_32] = { "_irq_elx_32" },
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[EXC_FIQ_ELX_32] = { "_fiq_elx_32" },
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[EXC_SERROR_ELX_32] = {"_serror_elx_32"},
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static const char *exception_names[NUM_EXC_VIDS] = {
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[EXC_VID_CUR_SP_EL0_SYNC] = "_sync_sp_el0",
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[EXC_VID_CUR_SP_EL0_IRQ] = "_irq_sp_el0",
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[EXC_VID_CUR_SP_EL0_FIRQ] = "_fiq_sp_el0",
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[EXC_VID_CUR_SP_EL0_SERR] = "_serror_sp_el0",
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[EXC_VID_CUR_SP_ELX_SYNC] = "_sync_sp_el3",
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[EXC_VID_CUR_SP_ELX_IRQ] = "_irq_sp_el3",
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[EXC_VID_CUR_SP_ELX_FIQ] = "_fiq_sp_el3",
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[EXC_VID_CUR_SP_ELX_SERR] = "_serror_sp_el3",
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[EXC_VID_LOW64_SYNC] = "_sync_elx_64",
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[EXC_VID_LOW64_IRQ] = "_irq_elx_64",
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[EXC_VID_LOW64_FIQ] = "_fiq_elx_64",
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[EXC_VID_LOW64_SERR] = "_serror_elx_64",
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[EXC_VID_LOW32_SYNC] = "_sync_elx_32",
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[EXC_VID_LOW32_IRQ] = "_irq_elx_32",
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[EXC_VID_LOW32_FIQ] = "_fiq_elx_32",
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[EXC_VID_LOW32_SERR] = "_serror_elx_32"
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};
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static void print_regs(struct exc_state *exc_state)
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@ -98,39 +72,122 @@ static void print_regs(struct exc_state *exc_state)
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printk(BIOS_DEBUG, "X%02d = 0x%016llx\n", i, regs->x[i]);
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}
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void exc_dispatch(struct exc_state *exc_state, uint64_t idx)
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static struct exception_handler *handlers[NUM_EXC_VIDS];
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int exception_handler_register(uint64_t vid, struct exception_handler *h)
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{
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if (idx >= EXC_COUNT) {
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printk(BIOS_DEBUG, "Bad exception index %lx.\n",
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(unsigned long)idx);
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} else {
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struct exception_handler_info *info = &exceptions[idx];
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if (vid >= NUM_EXC_VIDS)
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return -1;
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if (info->name)
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printk(BIOS_DEBUG, "exception %s\n", info->name);
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else
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printk(BIOS_DEBUG, "exception _not_used.\n");
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/* Just place at head of queue. */
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h->next = handlers[vid];
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store_release(&handlers[vid], h);
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return 0;
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}
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int exception_handler_unregister(uint64_t vid, struct exception_handler *h)
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{
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struct exception_handler *cur;
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struct exception_handler **prev;
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if (vid >= NUM_EXC_VIDS)
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return -1;
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prev = &handlers[vid];
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for (cur = handlers[vid]; cur != NULL; cur = cur->next) {
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if (cur != h)
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continue;
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/* Update previous pointer. */
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store_release(prev, cur->next);
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return 0;
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}
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print_regs(exc_state);
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if (test_exc) {
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exc_state->elx.elr += 4;
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raw_write_elr_current(exc_state->elx.elr);
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test_exc = 0;
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printk(BIOS_DEBUG, "new ELR = 0x%016llx\n", exc_state->elx.elr);
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} else
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die("exception");
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/* Not found */
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return -1;
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}
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exc_exit(&exc_state->regs);
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static void print_exception_info(struct exc_state *state, uint64_t idx)
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{
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if (idx < NUM_EXC_VIDS)
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printk(BIOS_DEBUG, "exception %s\n", exception_names[idx]);
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print_regs(state);
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}
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static void print_exception_and_die(struct exc_state *state, uint64_t idx)
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{
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print_exception_info(state, idx);
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die("exception death");
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}
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static int handle_exception(struct exc_state *state, uint64_t idx)
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{
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int ret = EXC_RET_ABORT;
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struct exception_handler *h;
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for (h = handlers[idx]; h != NULL; h = h->next) {
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int hret;
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hret = h->handler(state, idx);
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if (hret > ret)
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ret = hret;
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}
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return ret;
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}
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void exc_dispatch(struct exc_state *state, uint64_t idx)
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{
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int ret;
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if (idx >= NUM_EXC_VIDS) {
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printk(BIOS_DEBUG, "Bad exception index %x.\n", (int)idx);
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print_exception_and_die(state, idx);
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}
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ret = handle_exception(state, idx);
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if (ret == EXC_RET_ABORT)
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print_exception_and_die(state, idx);
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if (ret == EXC_RET_IGNORED || ret == EXC_RET_HANDLED_DUMP_STATE)
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print_exception_info(state, idx);
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exc_exit(&state->regs);
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}
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static int test_exception_handler(struct exc_state *state, uint64_t vector_id)
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{
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/* Update instruction pointer to next instrution. */
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state->elx.elr += sizeof(uint32_t);
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raw_write_elr_current(state->elx.elr);
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return EXC_RET_HANDLED;
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}
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static uint64_t test_exception(void)
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{
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uint64_t *a = (uint64_t *)0xfffffffff0000000ULL;
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struct exception_handler sync_elx;
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struct exception_handler sync_el0;
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unsigned long long *a = (void *)0xffffffff00000000ULL;
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test_exc = 1;
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sync_elx.handler = &test_exception_handler;
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sync_el0.handler = &test_exception_handler;
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printk(BIOS_DEBUG, "%llx\n", *a);
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exception_handler_register(EXC_VID_CUR_SP_ELX_SYNC, &sync_elx);
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exception_handler_register(EXC_VID_CUR_SP_EL0_SYNC, &sync_el0);
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force_read(*a);
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exception_handler_unregister(EXC_VID_CUR_SP_ELX_SYNC, &sync_elx);
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exception_handler_unregister(EXC_VID_CUR_SP_EL0_SYNC, &sync_el0);
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return 0;
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}
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@ -42,6 +42,24 @@
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#define STACK_POP_BYTES 16
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#define STACK_PUSH_BYTES -16
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#define EXC_VID_CUR_SP_EL0_SYNC 0
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#define EXC_VID_CUR_SP_EL0_IRQ 1
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#define EXC_VID_CUR_SP_EL0_FIRQ 2
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#define EXC_VID_CUR_SP_EL0_SERR 3
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#define EXC_VID_CUR_SP_ELX_SYNC 4
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#define EXC_VID_CUR_SP_ELX_IRQ 5
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#define EXC_VID_CUR_SP_ELX_FIQ 6
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#define EXC_VID_CUR_SP_ELX_SERR 7
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#define EXC_VID_LOW64_SYNC 8
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#define EXC_VID_LOW64_IRQ 9
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#define EXC_VID_LOW64_FIQ 10
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#define EXC_VID_LOW64_SERR 11
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#define EXC_VID_LOW32_SYNC 12
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#define EXC_VID_LOW32_IRQ 13
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#define EXC_VID_LOW32_FIQ 14
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#define EXC_VID_LOW32_SERR 15
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#define NUM_EXC_VIDS 16
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#ifndef __ASSEMBLY__
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#include <stdint.h>
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@ -30,8 +30,39 @@
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#ifndef _ARCH_EXCEPTION_H
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#define _ARCH_EXCEPTION_H
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#include <arch/transition.h>
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/* Initialize the exception handling on the current CPU. */
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void exception_hwinit(void);
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void exception_init(void);
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/*
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* Order matters for handling return values. The larger the value the higher
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* the precedence.
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*/
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enum {
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EXC_RET_IGNORED,
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EXC_RET_ABORT,
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EXC_RET_HANDLED,
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EXC_RET_HANDLED_DUMP_STATE,
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};
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struct exception_handler {
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int (*handler)(struct exc_state *state, uint64_t vector_id);
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struct exception_handler *next;
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};
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/*
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* Register a handler provided with the associated vector id. Returns 0 on
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* sucess, < 0 on error. Note that registration is not thread/interrupt safe.
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*/
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int exception_handler_register(uint64_t vid, struct exception_handler *h);
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/*
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* Unregister a handler from the vector id. Return 0 on success, < 0 on error.
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* Note that the unregistration is not thread/interrupt safe.
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*/
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int exception_handler_unregister(uint64_t vid, struct exception_handler *h);
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#endif
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@ -77,22 +77,22 @@
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*/
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ENTRY_WITH_ALIGN(exc_vectors, 11)
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eentry sync_curr_sp0,#0
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eentry irq_curr_sp0,#1
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eentry fiq_curr_sp0,#2
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eentry serror_curr_sp0,#3
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eentry sync_curr_spx,#4
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eentry irq_curr_spx,#5
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eentry fiq_curr_spx,#6
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eentry serror_curr_spx,#7
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eentry sync_lower_64,#8
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eentry irq_lower_64,#9
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eentry fiq_lower_64,#10
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eentry serror_lower_64,#11
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eentry sync_lower_32,#12
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eentry irq_lower_32,#13
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eentry fiq_lower_32,#14
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eentry serror_lower_32,#15
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eentry sync_curr_sp0, #EXC_VID_CUR_SP_EL0_SYNC
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eentry irq_curr_sp0, #EXC_VID_CUR_SP_EL0_IRQ
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eentry fiq_curr_sp0, #EXC_VID_CUR_SP_EL0_FIRQ
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eentry serror_curr_sp0, #EXC_VID_CUR_SP_EL0_SERR
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eentry sync_curr_spx, #EXC_VID_CUR_SP_ELX_SYNC
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eentry irq_curr_spx, #EXC_VID_CUR_SP_ELX_IRQ
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eentry fiq_curr_spx, #EXC_VID_CUR_SP_ELX_FIQ
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eentry serror_curr_spx, #EXC_VID_CUR_SP_ELX_SERR
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eentry sync_lower_64, #EXC_VID_LOW64_SYNC
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eentry irq_lower_64, #EXC_VID_LOW64_IRQ
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eentry fiq_lower_64, #EXC_VID_LOW64_FIQ
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eentry serror_lower_64, #EXC_VID_LOW64_SERR
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eentry sync_lower_32, #EXC_VID_LOW32_SYNC
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eentry irq_lower_32, #EXC_VID_LOW32_IRQ
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eentry fiq_lower_32, #EXC_VID_LOW32_FIQ
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eentry serror_lower_32, #EXC_VID_LOW32_SERR
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ENDPROC(exc_vectors)
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