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soc/intel/braswell: Unify DPTF enablement 

Currently, there are 3 separate settings for DPTF which are not always
in sync:
- the enabled/disabled state of the devicetree PCI device
- the 'dptf_enable' register, which sets the ACPI device status via GNVS
- the 'DptfDisable' register, which sets the FSP UPD of the same name

To make things sane, drop the two chip registers, and set the GNVS
variable and FSP UPD based on the enabled/disabled status of the DPTF
PCI device in the mainboard's devicetree.

TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI
devices are present/enabled when DPTF is enabled in devicetree, and not
present/disabled when disabled in devicetree.

Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Matt DeVillier 2023-10-27 15:18:22 -05:00 committed by Matt DeVillier
parent 96a7d9e76b
commit 4f961371a5
8 changed files with 4 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/facebook/fbg1701/devicetree.cb
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@ -62,7 +62,6 @@ chip soc/intel/braswell
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
register "PcdSdDetectChk" = "0" # Disable SD card detect
register "DptfDisable" = "1"
# LPE audio codec settings
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock

4
src/mainboard/google/cyan/devicetree.cb
View File

@ -77,8 +77,6 @@ chip soc/intel/braswell
# LPE audio codec settings
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
register "dptf_enable" = "true"
# Enable LPSS and LPE devices in ACPI mode
register "lpss_acpi_mode" = "1"
register "emmc_acpi_mode" = "0"
@ -97,7 +95,7 @@ chip soc/intel/braswell
device pci 00.0 on end # 8086 2280 - SoC transaction router
device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
device pci 03.0 off end # 8086 22b8 - Camera and Image Processor
device pci 0b.0 off end # 8086 22dc - Signal Processing Controller
device pci 0b.0 on end # 8086 22dc - PUNIT/DPTF
device pci 10.0 on end # 8086 2294 - MMC Port
device pci 11.0 off end # 8086 0F15 - SDIO Port
device pci 12.0 on end # 8086 0F16 - SD Port

4
src/mainboard/intel/strago/devicetree.cb
View File

@ -66,8 +66,6 @@ chip soc/intel/braswell
# LPE audio codec settings
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock
register "dptf_enable" = "true"
# Enable devices in ACPI mode
register "lpss_acpi_mode" = "1"
register "emmc_acpi_mode" = "1"
@ -86,7 +84,7 @@ chip soc/intel/braswell
device pci 00.0 on end # 8086 2280 - SoC transaction router
device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display
device pci 03.0 off end # 8086 22b8 - Camera and Image Processor
device pci 0b.0 on end # 8086 22dc - ?
device pci 0b.0 on end # 8086 22dc - PUNIT/DPTF
device pci 10.0 on end # 8086 2294 - MMC Port
device pci 11.0 off end # 8086 0F15 - SDIO Port
device pci 12.0 on end # 8086 0F16 - SD Port

1
src/mainboard/portwell/m107/devicetree.cb
View File

@ -62,7 +62,6 @@ chip soc/intel/braswell
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
register "PcdSdDetectChk" = "0" # Disable SD card detect
register "DptfDisable" = "1"
# LPE audio codec settings
register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock

1
src/mainboard/protectli/vault_bsw/devicetree.cb
View File

@ -62,7 +62,6 @@ chip soc/intel/braswell
register "ISPEnable" = "0" # Disable IUNIT
register "ISPPciDevConfig" = "3"
register "PcdSdDetectChk" = "0" # Disable SD card detect
register "DptfDisable" = "1"
# Enable devices in PCI mode
register "lpss_acpi_mode" = "0"

4
src/soc/intel/braswell/acpi.c
View File

@ -70,9 +70,7 @@ size_t size_of_dnvs(void)
void soc_fill_gnvs(struct global_nvs *gnvs)
{
const struct soc_intel_braswell_config *config = config_of_soc();
gnvs->dpte = config->dptf_enable;
gnvs->dpte = is_devfn_enabled(PCI_DEVFN(PUNIT_DEV, 0));
/* Fill in the Wi-Fi Region ID */
if (CONFIG(HAVE_REGULATORY_DOMAIN))

2
src/soc/intel/braswell/chip.c
View File

@ -79,7 +79,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->AzaliaConfigPtr = 0;
params->PunitPwrConfigDisable = config->PunitPwrConfigDisable;
params->ChvSvidConfig = config->ChvSvidConfig;
params->DptfDisable = config->DptfDisable;
params->DptfDisable = !is_devfn_enabled(PCI_DEVFN(PUNIT_DEV, 0));
params->PcdEmmcMode = config->PcdEmmcMode;
params->PcdUsb3ClkSsc = 1;
params->PcdDispClkSsc = 1;

3
src/soc/intel/braswell/chip.h
View File

@ -42,8 +42,6 @@ enum usb_comp_bg_value {
struct soc_intel_braswell_config {
bool enable_xdp_tap;
bool dptf_enable;
enum serirq_mode serirq_mode;
/* Disable SLP_X stretching after SUS power well loss */
@ -104,7 +102,6 @@ struct soc_intel_braswell_config {
uint8_t PcdEnableI2C6;
uint8_t PunitPwrConfigDisable;
uint8_t ChvSvidConfig;
uint8_t DptfDisable;
uint8_t PcdEmmcMode;
uint8_t Usb2Port0PerPortPeTxiSet;
uint8_t Usb2Port0PerPortTxiSet;