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mb/google/poppy/variants/nocturne: enable FPMCU power 

Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.

BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.

Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nick Vaccaro 2018-07-26 19:28:03 -07:00 committed by Patrick Georgi
parent d091cd1fc1
commit 4f9ff53e42
2 changed files with 3 additions and 10 deletions
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9
src/mainboard/google/poppy/variants/nocturne/devicetree.cb
View File

@ -423,15 +423,8 @@ chip soc/intel/skylake
register "compat_string" = ""google,cros-ec-spi""
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C11_IRQ)"
register "wake" = "GPE0_DW0_09" # GPP_C9
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
register "reset_delay_ms" = "0"
register "reset_off_delay_ms" = "0"
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)"
register "enable_delay_ms" = "0"
register "enable_off_delay_ms" = "0"
register "has_power_resource" = "1"
device spi 0 on end
end
end # FPMCU
end # GSPI #1
device pci 1e.4 on end # eMMC
device pci 1e.5 off end # SDIO

4
src/mainboard/google/poppy/variants/nocturne/gpio.c
View File

@ -38,7 +38,7 @@ static const struct pad_config gpio_table[] = {
/* A10 : CLKOUT_LPC1 ==> NC */
PAD_CFG_NC(GPP_A10),
/* A11 : PCH_FP_PWR_EN */
PAD_CFG_GPO(GPP_A11, 0, DEEP),
PAD_CFG_GPO(GPP_A11, 1, DEEP),
/* A12 : ISH_GP6 */
PAD_CFG_NC(GPP_A12),
/* A13 : SUSWARN# ==> SUSWARN_L */
@ -133,7 +133,7 @@ static const struct pad_config gpio_table[] = {
/* C9 : UART0_TXD ==> FPMCU_INT */
PAD_CFG_GPI_ACPI_SCI(GPP_C9, NONE, DEEP, INVERT),
/* C10 : UART0_RTS# ==> PCH_FPMCU_RST_ODL */
PAD_CFG_GPO(GPP_C10, 0, DEEP),
PAD_CFG_GPO(GPP_C10, 1, DEEP),
/* C11 : UART0_CTS# ==> FPMCU_INT */
PAD_CFG_GPI_APIC(GPP_C11, 20K_PU, DEEP),
/* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */