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soc/intel/uart: Drop SoC callback soc_uart_console_to_device

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This change renames `struct uart_gpio_pad_config` to `struct
uart_controller_config` and adds a new parameter devfn (which expects
devfn for the UART controller corresponding to the index in
PCI_DEVFN() format). This gets rid of the SoC callback to get `struct
device` pointer to the UART controller device.

Change-Id: Id0712a0038f2cc1a61b8b5a58fa155f14e7949a5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49212
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Furquan Shaikh 2021-01-06 20:30:35 -08:00 committed by Patrick Georgi
parent b1fa231d76
commit 4fa183fe79
10 changed files with 49 additions and 194 deletions
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26
src/soc/intel/alderlake/uart.c
View file

@ -17,9 +17,10 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
const struct uart_gpio_pad_config uart_gpio_pads[] = {
const struct uart_controller_config uart_ctrlr_config[] = {
{
.console_index = 0,
.devfn = PCH_DEVFN_UART0,
.gpios = {
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */
@ -27,6 +28,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 1,
.devfn = PCH_DEVFN_UART1,
.gpios = {
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
@ -34,6 +36,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 2,
.devfn = PCH_DEVFN_UART2,
.gpios = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
@ -41,23 +44,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
}
};
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
{
/*
* if index is valid, this function will return corresponding structure
* for uart console else will return NULL.
*/
switch (uart_console) {
case 0:
return pcidev_path_on_root(PCH_DEVFN_UART0);
case 1:
return pcidev_path_on_root(PCH_DEVFN_UART1);
case 2:
return pcidev_path_on_root(PCH_DEVFN_UART2);
default:
printk(BIOS_ERR, "Invalid UART console index\n");
return NULL;
}
}
const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config);

31
src/soc/intel/apollolake/uart.c
View file

@ -11,11 +11,11 @@
#include <soc/gpio.h>
#include <soc/pci_devs.h>
/* UART pad configuration. Support RXD and TXD for now. */
const struct uart_gpio_pad_config uart_gpio_pads[] = {
const struct uart_controller_config uart_ctrlr_config[] = {
#if CONFIG(SOC_INTEL_GEMINILAKE)
{
.console_index = 0,
.devfn = PCH_DEVFN_UART0,
.gpios = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, NATIVE, DEEP, NF1,
HIZCRx1, DISPUPD), /* LPSS_UART0_RXD */
@ -26,6 +26,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 2,
.devfn = PCH_DEVFN_UART2,
.gpios = {
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, NATIVE, DEEP, NF1,
HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
@ -36,6 +37,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
#else
{
.console_index = 0,
.devfn = PCH_DEVFN_UART0,
.gpios = {
PAD_CFG_NF(GPIO_38, NATIVE, DEEP, NF1), /* UART0 RX */
PAD_CFG_NF(GPIO_39, NATIVE, DEEP, NF1), /* UART0 TX */
@ -43,6 +45,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 1,
.devfn = PCH_DEVFN_UART1,
.gpios = {
PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */
@ -50,6 +53,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 2,
.devfn = PCH_DEVFN_UART2,
.gpios = {
PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */
@ -58,25 +62,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
#endif
};
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
{
/*
* if index is valid, this function will return corresponding structure
* for uart console else will return NULL.
*/
switch (uart_console) {
case 0:
return pcidev_path_on_root(PCH_DEVFN_UART0);
case 1:
return pcidev_path_on_root(PCH_DEVFN_UART1);
case 2:
return pcidev_path_on_root(PCH_DEVFN_UART2);
case 3:
return pcidev_path_on_root(PCH_DEVFN_UART3);
default:
printk(BIOS_ERR, "Invalid UART console index\n");
return NULL;
}
}
const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config);

26
src/soc/intel/cannonlake/uart.c
View file

@ -11,9 +11,10 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
const struct uart_gpio_pad_config uart_gpio_pads[] = {
const struct uart_controller_config uart_ctrlr_config[] = {
{
.console_index = 0,
.devfn = PCH_DEVFN_UART0,
.gpios = {
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
@ -21,6 +22,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 1,
.devfn = PCH_DEVFN_UART1,
.gpios = {
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
@ -28,6 +30,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 2,
.devfn = PCH_DEVFN_UART2,
.gpios = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
@ -35,23 +38,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
}
};
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
{
/*
* if index is valid, this function will return corresponding structure
* for uart console else will return NULL.
*/
switch (uart_console) {
case 0:
return pcidev_path_on_root(PCH_DEVFN_UART0);
case 1:
return pcidev_path_on_root(PCH_DEVFN_UART1);
case 2:
return pcidev_path_on_root(PCH_DEVFN_UART2);
default:
printk(BIOS_ERR, "Invalid UART console index\n");
return NULL;
}
}
const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config);

21
src/soc/intel/common/block/include/intelblocks/uart.h
View file

@ -10,8 +10,10 @@
#define MAX_GPIO_PAD_PER_UART 2
struct uart_gpio_pad_config {
struct uart_controller_config {
int console_index;
/* devfn in PCI_DEVFN() format */
unsigned int devfn;
struct pad_config gpios[MAX_GPIO_PAD_PER_UART];
};
@ -55,21 +57,4 @@ void uart_bootblock_init(void);
*/
const struct device *uart_get_device(void);
/**************************** SoC callbacks ***********************************/
/*
* SoC should implement soc_uart_console_to_device() function to
* get UART debug controller device structure based on console number
* Caller needs to check proper UART console index supported by SoC.
* If wrong UART console index is passed to function, it'll return NULL.
*
* Input:
* UART console index selected in config
*
* Returns:
* Pointer to device structure = If device has a UART debug controller.
* NULL = otherwise
*/
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console);
#endif /* SOC_INTEL_COMMON_BLOCK_UART_H */

8
src/soc/intel/common/block/uart/uart.c
View file

@ -20,7 +20,7 @@
#define UART_PCI_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)
#define UART_CONSOLE_INVALID_INDEX 0xFF
extern const struct uart_gpio_pad_config uart_gpio_pads[];
extern const struct uart_controller_config uart_ctrlr_config[];
extern const int uart_max_index;
static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr)
@ -50,7 +50,7 @@ static int uart_get_valid_index(void)
int index;
for (index = 0; index < uart_max_index; index++) {
if (uart_gpio_pads[index].console_index ==
if (uart_ctrlr_config[index].console_index ==
CONFIG_UART_FOR_CONSOLE)
return index;
}
@ -88,7 +88,7 @@ const struct device *uart_get_device(void)
int console_index = uart_get_valid_index();
if (console_index != UART_CONSOLE_INVALID_INDEX)
return soc_uart_console_to_device(CONFIG_UART_FOR_CONSOLE);
return pcidev_path_on_root(uart_ctrlr_config[console_index].devfn);
else
return NULL;
}
@ -123,7 +123,7 @@ static void uart_configure_gpio_pads(void)
int index = uart_get_valid_index();
if (index != UART_CONSOLE_INVALID_INDEX)
gpio_configure_pads(uart_gpio_pads[index].gpios,
gpio_configure_pads(uart_ctrlr_config[index].gpios,
MAX_GPIO_PAD_PER_UART);
}

26
src/soc/intel/elkhartlake/uart.c
View file

@ -11,9 +11,10 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
const struct uart_gpio_pad_config uart_gpio_pads[] = {
const struct uart_controller_config uart_ctrlr_config[] = {
{
.console_index = 0,
.devfn = PCH_DEVFN_UART0,
.gpios = {
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
@ -21,6 +22,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 1,
.devfn = PCH_DEVFN_UART1,
.gpios = {
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
@ -28,6 +30,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 2,
.devfn = PCH_DEVFN_UART2,
.gpios = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
@ -35,23 +38,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
}
};
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
{
/*
* if index is valid, this function will return corresponding structure
* for uart console else will return NULL.
*/
switch (uart_console) {
case 0:
return pcidev_path_on_root(PCH_DEVFN_UART0);
case 1:
return pcidev_path_on_root(PCH_DEVFN_UART1);
case 2:
return pcidev_path_on_root(PCH_DEVFN_UART2);
default:
printk(BIOS_ERR, "Invalid UART console index\n");
return NULL;
}
}
const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config);

26
src/soc/intel/icelake/uart.c
View file

@ -11,9 +11,10 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
const struct uart_gpio_pad_config uart_gpio_pads[] = {
const struct uart_controller_config uart_ctrlr_config[] = {
{
.console_index = 0,
.devfn = PCH_DEVFN_UART0,
.gpios = {
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
@ -21,6 +22,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 1,
.devfn = PCH_DEVFN_UART1,
.gpios = {
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
@ -28,6 +30,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 2,
.devfn = PCH_DEVFN_UART2,
.gpios = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
@ -35,23 +38,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
}
};
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
{
/*
* if index is valid, this function will return corresponding structure
* for uart console else will return NULL.
*/
switch (uart_console) {
case 0:
return pcidev_path_on_root(PCH_DEVFN_UART0);
case 1:
return pcidev_path_on_root(PCH_DEVFN_UART1);
case 2:
return pcidev_path_on_root(PCH_DEVFN_UART2);
default:
printk(BIOS_ERR, "Invalid UART console index\n");
return NULL;
}
}
const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config);

26
src/soc/intel/jasperlake/uart.c
View file

@ -11,9 +11,10 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
const struct uart_gpio_pad_config uart_gpio_pads[] = {
const struct uart_controller_config uart_ctrlr_config[] = {
{
.console_index = 0,
.devfn = PCH_DEVFN_UART0,
.gpios = {
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
@ -21,6 +22,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 1,
.devfn = PCH_DEVFN_UART1,
.gpios = {
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
@ -28,6 +30,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 2,
.devfn = PCH_DEVFN_UART2,
.gpios = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
@ -35,23 +38,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
}
};
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
{
/*
* if index is valid, this function will return corresponding structure
* for uart console else will return NULL.
*/
switch (uart_console) {
case 0:
return pcidev_path_on_root(PCH_DEVFN_UART0);
case 1:
return pcidev_path_on_root(PCH_DEVFN_UART1);
case 2:
return pcidev_path_on_root(PCH_DEVFN_UART2);
default:
printk(BIOS_ERR, "Invalid UART console index\n");
return NULL;
}
}
const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config);

27
src/soc/intel/skylake/uart.c
View file

@ -10,10 +10,10 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
/* UART pad configuration. Support RXD and TXD for now. */
const struct uart_gpio_pad_config uart_gpio_pads[] = {
const struct uart_controller_config uart_ctrlr_config[] = {
{
.console_index = 0,
.devfn = PCH_DEVFN_UART0,
.gpios = {
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
@ -21,6 +21,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 1,
.devfn = PCH_DEVFN_UART1,
.gpios = {
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
@ -28,6 +29,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 2,
.devfn = PCH_DEVFN_UART2,
.gpios = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
@ -35,23 +37,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
}
};
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
{
/*
* if index is valid, this function will return corresponding structure
* for uart console else will return NULL.
*/
switch (uart_console) {
case 0:
return pcidev_path_on_root(PCH_DEVFN_UART0);
case 1:
return pcidev_path_on_root(PCH_DEVFN_UART1);
case 2:
return pcidev_path_on_root(PCH_DEVFN_UART2);
default:
printk(BIOS_ERR, "Invalid UART console index\n");
return NULL;
}
}
const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config);

26
src/soc/intel/tigerlake/uart.c
View file

@ -17,9 +17,10 @@
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
const struct uart_gpio_pad_config uart_gpio_pads[] = {
const struct uart_controller_config uart_ctrlr_config[] = {
{
.console_index = 0,
.devfn = PCH_DEVFN_UART0,
.gpios = {
PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
@ -27,6 +28,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 1,
.devfn = PCH_DEVFN_UART1,
.gpios = {
PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* UART1 RX */
PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), /* UART1 TX */
@ -34,6 +36,7 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
},
{
.console_index = 2,
.devfn = PCH_DEVFN_UART2,
.gpios = {
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2 RX */
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2 TX */
@ -41,23 +44,4 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = {
}
};
const int uart_max_index = ARRAY_SIZE(uart_gpio_pads);
DEVTREE_CONST struct device *soc_uart_console_to_device(int uart_console)
{
/*
* if index is valid, this function will return corresponding structure
* for uart console else will return NULL.
*/
switch (uart_console) {
case 0:
return pcidev_path_on_root(PCH_DEVFN_UART0);
case 1:
return pcidev_path_on_root(PCH_DEVFN_UART1);
case 2:
return pcidev_path_on_root(PCH_DEVFN_UART2);
default:
printk(BIOS_ERR, "Invalid UART console index\n");
return NULL;
}
}
const int uart_max_index = ARRAY_SIZE(uart_ctrlr_config);